Liveness in Timed and Untimed Systems

We present a coordinated pair of general labeled transition system models for describing timed and untimed concurrent systems. Both of the models incorporate liveness properties as well as safety properties. The models are related via an embedding of the untimed model into the timed model, which preserves all the interesting attributes of the untimed model. Both models include notions of environment-freedom, which express the idea that the liveness properties can be guaranteed by the system, independently of the behavior of the environment in which it operates. These environment-freedom conditions are used to prove compositionality results for both models. This pair of models, which generalize several existing models, is intended to comprise a general formalism for the verification of timed and untimed concurrent systems.

[1]  G. G. Stokes "J." , 1890, The New Yale Book of Quotations.

[2]  D. Belsnes Single-Message Communication , 1976, IEEE Trans. Commun..

[3]  C. A. R. Hoare,et al.  Communicating sequential processes , 1978, CACM.

[4]  C.A. Vissers,et al.  Formal description techniques , 1983, Proceedings of the IEEE.

[5]  Rocco De Nicola,et al.  Testing Equivalences for Processes , 1984, Theor. Comput. Sci..

[6]  Bowen Alpern,et al.  Defining Liveness , 1984, Inf. Process. Lett..

[7]  Editors , 1986, Brain Research Bulletin.

[8]  Nancy A. Lynch,et al.  Hierarchical correctness proofs for distributed algorithms , 1987, PODC '87.

[9]  Frank Thomson Leighton,et al.  Trace Theory for Automatic Hierarchical Verification of Speed-Independent Circuits , 1988 .

[10]  Nancy A. Lynch,et al.  A Proof of the Kahn Principle for Input/Output Automata , 1989, Inf. Comput..

[11]  David L. Dill,et al.  Trace theory for automatic hierarchical verification of speed-independent circuits , 1989, ACM distinguished dissertations.

[12]  Frank Dederichs,et al.  Safety and Liveness From a Methodological Point of View , 1990, Inf. Process. Lett..

[13]  Joseph Sifakis,et al.  An Overview and Synthesis on Timed Process Algebras , 1991, CAV.

[14]  Joseph Sifakis,et al.  An Overview and Synthesis on Timed Process Algebras , 1991, REX Workshop.

[15]  Nancy A. Lynch,et al.  Forward and Backward Simulations, II: Timing-Based Systems , 1991, Inf. Comput..

[16]  Zohar Manna,et al.  From Timed to Hybrid Systems , 1991, REX Workshop.

[17]  Da-Wei Wang,et al.  Games I/O Automata Play (Extended Abstract) , 1992, CONCUR.

[18]  F. Vaandrager Forward and Backward Simulations Part I : Untimed Systems , 1993 .

[19]  Nancy A. Lynch,et al.  Simulation Techniques for Proving Properties of Real-Time Systems , 1993, REX School/Symposium.

[20]  Martín Abadi,et al.  Composing specifications , 1989, TOPL.

[21]  Nancy A. Lynch,et al.  Correctness of At-Most-Once Message Delivery Protocols , 1993, FORTE.

[22]  Nancy A. Lynch,et al.  Forward and backward simulations, part II: timing-based systems , 1993 .

[23]  J. S gaard-Andersen,et al.  Correctness of Communications Protocols, A case Study , 1993 .

[24]  Leslie Lamport,et al.  The temporal logic of actions , 1994, TOPL.

[25]  F. Vaandrager,et al.  Verification of an Audio Control Protocol , 1994, FTRTFT.

[26]  Martín Abadi,et al.  An old-fashioned recipe for real time , 1994, TOPL.

[27]  Nancy A. Lynch,et al.  Forward and Backward Simulations: I. Untimed Systems , 1995, Inf. Comput..

[28]  Frits W. Vaandrager,et al.  A Note on Fairness in I/O Automata , 1996, Inf. Process. Lett..