High-speed three-stage operational transconductance amplifiers for switched-capacitor circuits

In this paper, three-stage operational transconductance amplifiers (OTAs) for use in switched-capacitor (SC) circuits using nanometer CMOS technologies are described. Two three-stage OTAs, one with nested-Miller compensation (NMC) as a basic compensation scheme and another with damping factor control frequency compensation (DFCFC) as an advanced compensation scheme are presented. The open-loop small-signal analysis as well as the large signal-analysis for both OTAs are investigated and their speed performance is compared and discussed. Circuit level simulations are carried out using a 90 nm CMOS technology with HSPICE. Simulation results show that the NMC and the DFCFC OTAs achieve a settling time of 17.5 ns and 8.4 ns with 0.02% accuracy, respectively, while consuming 3 mW from a 1.2 V power supply and have the same input-referred thermal noise.

[1]  Siddharth Seth,et al.  Settling Time and Noise Optimization of a Three-Stage Operational Transconductance Amplifier , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  Boris Murmann,et al.  The Design of Fast-Settling Three-Stage Amplifiers Using the Open-Loop Damping Factor as a Design Parameter , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.

[3]  Mohammad Yavari,et al.  A Design Procedure for CMOS Three-Stage NMC Amplifiers , 2011, IEICE Trans. Fundam. Electron. Commun. Comput. Sci..

[4]  Byeong-Ha Park,et al.  A 9.43-ENOB 160MS/s 1.2V 65nm CMOS ADC based on multi-stage amplifiers , 2009, 2009 IEEE Custom Integrated Circuits Conference.

[5]  J. Huijsing,et al.  Design of low-voltage, low-power operational amplifier cells , 1996 .

[6]  E. Sánchez-Sinencio,et al.  Multistage amplifier topologies with nested Gm-C compensation , 1997, IEEE J. Solid State Circuits.

[7]  Hoi Lee,et al.  Active-feedback frequency-compensation technique for low-power multistage amplifiers , 2003, IEEE J. Solid State Circuits.

[8]  Ka Nang Leung,et al.  Three-stage large capacitive load amplifier with damping-factor-control frequency compensation , 2000, IEEE Journal of Solid-State Circuits.

[9]  Ka Nang Leung,et al.  Right-half-plane zero removal technique for low-voltage low-power nested Miller compensation CMOS amplifier , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[10]  Gaetano Palumbo,et al.  Design methodology and advances in nested-Miller compensation , 2002 .

[11]  Qing Wang,et al.  Global chemical profiling based quality evaluation approach of rhubarb using ultra performance liquid chromatography with tandem quadrupole time-of-flight mass spectrometry. , 2015, Journal of separation science.

[12]  Young-Ju Kim,et al.  A 10-b 120-MS/s 45 nm CMOS ADC using a re-configurable three-stage switched amplifier , 2012 .

[13]  Andrea Pugliese,et al.  Nested Miller compensation capacitor sizing rules for fast-settling amplifier design , 2005 .