TCPA editor: A design automation environment for a class of coarse-grained reconfigurable arrays

In the realm of heterogeneous Multi-Processor System-on-Chip (MPSoC) architectures, Coarse-Grained Reconfigurable Arrays (CGRAs) have emerged as a low-power and highly efficient solution for speeding up computations. However, designing such programmable hardware accelerators is a time consuming and non-trivial task. To ease the development process, we present the TCPA Editor: a Java-based graphical design environment for automatically generating Tightly Coupled Processor Arrays (TCPAs), a class of CGRAs that are highly parameterizable. The tool is tailored for designing, simulating, prototyping, and testing TCPA architectures. These consist of a massively parallel array of tightly coupled VLIW processing elements. The core array is complemented by peripheral components, e.g., controllers and a reconfigurable memory architecture. Based on the user's design entries, the editor generates synthesizable VHDL codes that describe each instance of a TCPA component. The editor can also be used for assembly programming and graphical interconnect setup. These configurations are combined into one binary code, which is used to reconfigure the hardware at runtime. Furthermore, the tool automatically generates synthesis parameters for today's de facto standard for on-chip communication. Hence, TCPAs can be easily interfaced to memory-mapped devices and high-speed streaming data, which allows for burst transfers of unrestricted size. The editor presents itself as a very powerful and user-friendly design tool for improving productivity. In the demonstration, we showcase our tool for the generation and system integration of TCPAs into heterogeneous MPSoC architectures. Finally, we present real-world case studies and synthesis results from different architectures prototyped in FPGA and ASIC technologies.