Eliminating the address translation bottleneck for physical address cache

Two architectural techniques are presented and analyzed in this paper that aim at eliminating the Translation Lc&aside Buffer (TLB) access delay from the critical path of physical address cache-based scalar processors. The first technique, parallel address translation, masks the TLB access delay by using a set-associative virtual memory map to extend the cache size beyond the product of the cache associativity and the virtual memory page size. The second teehnique, lazy address translation, bypasses the TLB access completely by using the base register and offset in a memory reference as a caching mechanism for its corresponding physical page. Consequently the TLB access is needed only when this caching scheme fails. A trace-driven simulation study is conducted and the experimental results show that under the given workload the padel address translation scheme works best when the virtual memory is 16way set associative, and the penalty on the average cycle-per-instruction (CPI) due to lazy address translation is less than 1.3%.