Modeling and Layout Optimization for On-chip Inductive Coupling

In this paper, we study the modeling and layout optimization for on-chip interconnect structures to minimize the inductive coupling. We first investigate the characteristics of m utual (as well as self) inductance for coplanar, micro-stri pline, and stripline structures, and examine the effectiveness of des ign freedoms such as wire sizing, spacing, and shielding. We then propose formula-based keff models as the figures of merit for inductive coupling in the th ree interconnect structures, and apply the proposed models to automatically synthesize on-c hip interconnect structures. Experiments show that compar ed to the coupling coefficients computed by a numerical field sol ver, thekeff models have about 15% difference for coplanar structures, and have negligible difference for micro-stri pline and stripline structures. In addition, interconnect structures meeting given noise specifications can be synthesized insta ntly using proposedkeff models. This work makes use of machines donated by Intel, whose gener ous donation is greatly appreciated. Related works and upda te on this work can be found at http://eda.ece.wisc.edu.