Design of an 8-wide superscalar RISC microprocessor with simultaneous multithreading

A 250M transistor microprocessor implements the Alpha instruction set and features 8-wide superscalar issue and simultaneous multithreading in a 0.125/spl mu/m SOI process. Performance is estimated at over three times that of the previous design.

[1]  Norman J. Rohrer,et al.  SOI circuit design concepts , 2000 .

[2]  A. Kumar,et al.  A 1.2 GHz Alpha microprocessor with 44.8 GB/s chip pin bandwidth , 2001, 2001 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC (Cat. No.01CH37177).

[3]  T. Fischer,et al.  Design tradeoffs in stall-control circuits for 600 MHz instruction queues , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).

[4]  Dean M. Tullsen,et al.  Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor , 1996, 23rd Annual International Symposium on Computer Architecture (ISCA'96).

[5]  S. Storino,et al.  A commercial multithreaded RISC processor , 1998, 1998 IEEE International Solid-State Circuits Conference. Digest of Technical Papers, ISSCC. First Edition (Cat. No.98CH36156).