A priori wiring estimations and optimal multilevel wiring networks for portable ULSI systems
暂无分享,去创建一个
[1] W. Donath. Wire length distribution for placements of computer logic , 1981 .
[2] P. Christie,et al. A fractal analysis of interconnection complexity , 1993, Proc. IEEE.
[3] Takayasu Sakurai,et al. Closed-form expressions for interconnection delay, coupling, and crosstalk in VLSIs , 1993 .
[4] Roy L. Russo,et al. On a Pin Versus Block Relationship For Partitions of Logic Graphs , 1971, IEEE Transactions on Computers.
[5] William E. Donath,et al. Placement and average interconnection lengths of computer logic , 1979 .
[6] H. B. Bakoglu,et al. Circuits, interconnections, and packaging for VLSI , 1990 .
[7] Farid N. Najm,et al. A survey of power estimation techniques in VLSI circuits , 1994, IEEE Trans. Very Large Scale Integr. Syst..
[8] R. W. Keyes,et al. The wire-limited logic chip , 1982 .
[9] A. Masaki,et al. Equations for Estimating Wire Length in Various Types of 2-D and 3-D System Packaging Structures , 1987 .
[10] G. A. Sai-Halasz,et al. Performance trends in high-end processors , 1995, Proc. IEEE.