Semiconductor memory device, having partial activation structure, capable page mode operation and Operation method there-of

This has enabled a partial structure capable of page mode operation the semiconductor memory device and its operation method is disclosed. The semiconductor memory device of the present invention comprises a memory cell array, a row decoder and word line driver, a column decoder, a row address comparator and the charge-free circuit. The memory cell array is divided into at least two column blocks, a column block is selected in response to the column block selection address. A row decoder (including the word line driver) and the column decoder selects the corresponding word line and a column line in a column block is selected in response to each row address and column address. The row address comparator is configured to receive a row address (hereinafter referred to as a first row address) is input and compared with the current row address (hereinafter referred to as a second row address) input previously. Free the charge circuit includes an active command is then automatically disables the word line activated after a predetermined time, that is the free car way, the same result of the comparison the first and the second row address of the row address comparator for the charge precharge of the active word line The block image. According to the present invention, there is an advantage that input and output speed and therefore the operation speed is faster improvement of the data for the memory cells having the same row address.