Estimation of maximum current envelope for power bus analysis and design
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[1] K. Cheng,et al. Vector Generation For Maximum Instantaneous Current Through Supply Lines For CMOS Circuits , 1997, Proceedings of the 34th Design Automation Conference.
[2] Robert K. Brayton,et al. Multilevel logic synthesis , 1990, Proc. IEEE.
[3] Ibrahim N. Hajj,et al. Maximum current estimation in CMOS circuits , 1992, [1992] Proceedings 29th ACM/IEEE Design Automation Conference.
[4] Ibrahim N. Hajj,et al. Resolving Signal Correlations for Estimating Maximum Currents in CMOS Combinational Circuits , 1993, 30th ACM/IEEE Design Automation Conference.
[5] Hendrikus J. M. Veendrick,et al. Short-circuit dissipation of static CMOS circuitry and its impact on the design of buffer circuits , 1984 .
[6] E. Loukakis,et al. An algorithm for the maximum internally stable set in a weighted graph , 1983 .
[7] S. Chowdhury,et al. Estimation of maximum currents in MOS IC logic circuits , 1990, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..
[8] David S. Johnson,et al. Computers and In stractability: A Guide to the Theory of NP-Completeness. W. H Freeman, San Fran , 1979 .