A novel start-controlled phase/frequency detector for multiphase-output delay-locked loops

In this paper, a novel start-controlled phase/frequency detector (PFD) for multiphase-output delay-locked loops (MODLLs) is presented. In the proposed PFD, the start-controlled circuit is used to provide a precise multiphase-output without the locking problem. The PFD utilizes a new NAND-resetable dynamic DFF so that a shorter reset path is achieved. Thus, lower power consumption and higher speed can be obtained. A MODLL using the proposed start-controlled PFD is post-layout simulated using the TSMC 0.35-/spl mu/m 2P4M CMOS process. The results show that the total delay time between the input and the output of the MODLL is just one clock cycle and all of the delay cells provide precise multiphase-output without false locking or harmonic locking. Compared to the static DFF based start-controlled PFD, the power consumption of the proposed NAND-resetable dynamic DFF based PFD is reduced at least 61%. The power consumption of the proposed start-controlled PFD is 100 /spl mu/W at 2V and 100MHz. The area of the MODLL circuit is 426 /spl mu/m /spl times/ 381 /spl mu/m.

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