论文信息 - A Low-Power High-Speed Self-Calibrated Differential Comparator

A Low-Power High-Speed Self-Calibrated Differential Comparator

A self-calibrated differential voltage comparator with a high speed/power ratio is presented. The comparator employs a triple differential input transconductance stage followed by a regenerative flip-flop and an output latch, and achieves a resolution of 1 mV at 40 MHz with less than 300 ¿W of total power dissipation. Fabricated in 1.2 ¿m CMOS technology, the circuit occupies 200 × 100 ¿m2 of silicon area.

C. Azeredo Leme | Jose Silva | Paulo Rodrigo | J.E. Franca

[1] J. H. Atherton,et al. An offset reduction technique for use with CMOS integrated comparators and amplifiers , 1992 .

[2] Jieh-Tsorng Wu,et al. A 100-MHz pipelined CMOS comparator , 1988 .

[3] F. O. Eynde,et al. A high-speed CMOS comparator with 8-b resolution , 1992 .