A Low-Power High-Speed Self-Calibrated Differential Comparator
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A self-calibrated differential voltage comparator with a high speed/power ratio is presented. The comparator employs a triple differential input transconductance stage followed by a regenerative flip-flop and an output latch, and achieves a resolution of 1 mV at 40 MHz with less than 300 ¿W of total power dissipation. Fabricated in 1.2 ¿m CMOS technology, the circuit occupies 200 × 100 ¿m2 of silicon area.
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