Efficient bit‐parallel subcircuit extraction using CUDA

Wafer processing technology has been improving rapidly. Moore's law has been exceeded as the number of transistors in a dense integrated circuit, now increases threefold or more, approximately every year. The integrated circuit has gone from very large scale to giga large scale. The extraction of subcircuits has therefore become computation‐intensive. In this paper, we propose an efficient bit‐parallel subcircuit extraction algorithm using graphic processing units. We conducted experimental trials and demonstrated that the proposed algorithm can achieve high throughput, suggesting practical applications in the extraction of subcircuits. Copyright © 2015 John Wiley & Sons, Ltd.

[1]  Che-Lun Hung,et al.  GPU‐UPGMA: high‐performance computing for UPGMA algorithm based on graphics processing units , 2015, Concurr. Comput. Pract. Exp..

[2]  N.K. Govindaraju,et al.  A Memory Model for Scientific Algorithms on Graphics Processors , 2006, ACM/IEEE SC 2006 Conference (SC'06).

[3]  Che-Lun Hung,et al.  An efficient parallel-network packet pattern-matching approach using GPUs , 2014, J. Syst. Archit..

[4]  Lei Xie,et al.  Detecting evolutionary relationships across existing fold space, using sequence order-independent profile–profile alignments , 2008, Proceedings of the National Academy of Sciences.

[5]  Chen-Yi Lee,et al.  A novel subcircuit extraction algorithm by recursive identification scheme , 2001, ISCAS 2001. The 2001 IEEE International Symposium on Circuits and Systems (Cat. No.01CH37196).

[6]  Carl Ebeling,et al.  SubGemini: Identifying SubCircuits using a Fast Subgraph Isomorphism Algorithm , 1993, 30th ACM/IEEE Design Automation Conference.

[7]  B. Noble,et al.  On certain integrals of Lipschitz-Hankel type involving products of bessel functions , 1955, Philosophical Transactions of the Royal Society of London. Series A, Mathematical and Physical Sciences.

[8]  Yaw-Ling Lin,et al.  Efficient GPGPU-Based Parallel Packet Classification , 2011, 2011IEEE 10th International Conference on Trust, Security and Privacy in Computing and Communications.

[9]  Narayanan Vijaykrishnan,et al.  SUBGEN: a genetic approach for subcircuit extraction , 1996, Proceedings of 9th International Conference on VLSI Design.

[10]  Nian Zhang,et al.  A Novel Subcircuit Extraction Algorithm Using Heuristic Dynamic Programming (HDP) , 2002 .

[11]  Naga K. Govindaraju,et al.  A Survey of General‐Purpose Computation on Graphics Hardware , 2007 .