Timing analysis and optimization for high-performance digital circuits

Meeting performance constraints in synchronous digital circuits is crucial since a violation may cause an unexpected value to be latched in a memory element. To guarantee the absence of timing violations the performance of a design needs to be estimated accurately and verified against given performance constraints. This delay estimation is called timing analysis. The main difficulty of timing analysis for gate-level digital circuits is the existence of false paths. A false path is a topological path of a given circuit along which a signal event never propagates. Since false paths do not contribute to the delay of a circuit, they need to be excluded when the performance of a circuit is estimated. Although false path detection has been researched extensively in the last decade, it has always been studied in a specific problem, namely arrival time analysis of combinational circuits, in which the arrival times of the outputs of a circuit are estimated given the arrival times of the inputs. The main contribution of the first part of this dissertation is to introduce and present algorithms for a new problem: false-path-aware required time analysis of combinational circuits, in which the required times of the inputs of a circuit are estimated given the required times of the outputs. This problem forms the core of a rich set of novel timing analysis problems arising in hierarchical designs. The applications include false path detection and removal of combinational circuits under unknown surrounding environments and hierarchical false-path-aware timing analysis. To meet an aggressive performance goal, timing optimization algorithms play a key role in exploring a design space systematically. The second part of the dissertation focuses on timing optimization in a logic synthesis step called technology mapping, where a technology-independent circuit is translated to a circuit composed only of gates in a given gate library. Although the complexity of the technology mapping problem for area minimization is well-understood, technology mapping for delay minimization has been tackled using heuristic approaches without knowing its exact complexity. The contribution of the second part of the dissertation is a linear-time algorithm that solves the problem optimally under a load-independent delay model. There is no need to resort to heuristic approaches since the problem can be solved optimally and efficiently.