Using embedded infrastructure IP for SOC post-silicon verification

This paper presents a method to embed an FPGA core in a SOC as an infrastructure IP that can exploit transaction-based verification methodology to verify and debug the first silicon. The primary objective for post-silicon verification is to reduce the time taken for validating the first silicon. Additionally, verifying silicon at chip-level is expected to speedup the silicon debugging and thus reduces the time to market. Experimental results presented in this paper demonstrate that the proposed method can be implemented with small overhead.