Dynamic threshold body- and gate-coupled SOI ESD protection networks 1 1997. Reprinted with permis
暂无分享,去创建一个
Ghavam G. Shahidi | Jack A. Mandelman | Steven H. Voldman | Fariborz Assaderaghi | Ghavam G. Shahidi | Louis L. Hsu | Fariborz Assaderaghi | Louis L. Hsu
[1] Chenming Hu. Low-voltage CMOS device scaling , 1994, Proceedings of IEEE International Solid-State Circuits Conference - ISSCC '94.
[2] Sung-Mo Kang,et al. EOS/ESD protection circuit design for deep submicron SOI technology , 1995, Electrical Overstress/Electrostatic Discharge Symposium Proceedings.
[3] G. Groeseneken,et al. Double snapback in SOI nMOSFETs and its application for SOI ESD protection , 1993, IEEE Electron Device Letters.
[4] J. Colinge. Silicon-on-Insulator Technology , 1991 .
[5] Tak H. Ning,et al. CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications , 1995, IBM Journal of Research and Development.
[6] S. Ramaswamy,et al. Heat flow analysis for EOS/ESD protection device design in SOI technology , 1997 .
[7] S. S. Yuen,et al. Comparison of ESD protection capability of SOI and bulk CMOS output buffers , 1994, Proceedings of 1994 IEEE International Reliability Physics Symposium.
[8] C. Duvvury,et al. ESD design for deep submicron SOI technology [NMOS transistor] , 1996, 1996 Symposium on VLSI Technology. Digest of Technical Papers.
[9] Chenming Hu,et al. A dynamic threshold voltage MOSFET (DTMOS) for ultra-low voltage operation , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.
[10] J.Y.-C. Sun,et al. CMOS-on-SOI ESD protection networks , 1996, 1996 Proceedings Electrical Overstress/Electrostatic Discharge Symposium.
[11] G. Groeseneken,et al. Analysis of Snapback in Soi nMosfets and its Use for an Soi Esd Protection Circuit , 1992, 1992 IEEE International SOI Conference.