40 Gb/s Transimpedance-AGC Amplifier and CDR Circuit for Broadband Data Receivers in 90 nm CMOS
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[1] J.D.H. Alexander. Clock recovery from random binary signals , 1975 .
[2] M. Kardos,et al. High-gain transimpedance amplifier in InP-based HBT technology for the receiver in 40-Gb/s optical-fiber TDM links , 2000, IEEE Journal of Solid-State Circuits.
[3] N. Tzartzanis,et al. A Reversible Poly-Phase Distributed VCO , 2006, 2006 IEEE International Solid State Circuits Conference - Digest of Technical Papers.
[4] J. Long,et al. A 10 Gb/s CDR/DEMUX with LC delay line VCO in 0.18 /spl mu/m CMOS , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).
[5] Liang-Hung Lu,et al. 40-Gb/s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-$\mu{\hbox {m}}$ CMOS , 2007, IEEE Journal of Solid-State Circuits.
[6] Eduard Säckinger. Broadband Circuits for Optical Fiber Communication: Säckinger/Broadband , 2005 .
[7] B. Razavi,et al. - Gb / s Limiting Amplifier and Laser / Modulator Driver in 0 . 18-m CMOS Technology , 2001 .
[8] S. Lipa,et al. Rotary traveling-wave oscillator arrays: a new clock technology , 2001 .
[9] E. Sackinger,et al. Broadband Circuits for Optical Fiber Communication , 2005 .
[10] Behzad Razavi,et al. 40-Gb/s amplifier and ESD protection circuit in 0.18-/spl mu/m CMOS technology , 2004, IEEE Journal of Solid-State Circuits.
[11] B. Razavi,et al. 10-Gb/s limiting amplifier and laser/modulator driver in 0.18-μm CMOS technology , 2003, IEEE J. Solid State Circuits.
[12] A. Leven,et al. An InGaAs-InP HBT differential transimpedance amplifier with 47-GHz bandwidth , 2003, IEEE Journal of Solid-State Circuits.
[13] Ali Hajimiri,et al. Capacity limits and matching properties of integrated capacitors , 2002, IEEE J. Solid State Circuits.
[14] Shen-Iuan Liu,et al. A 40Gb/s Transimpedance-AGC Amplifier with 19dB DR in 90nm CMOS , 2007, 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.
[15] Liang-Hung Lu,et al. 40-Gb / s High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0 . 18-m CMOS , 2009 .
[16] Sorin P. Voinigescu,et al. Erratum: 6-kΩ 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range (IEEE Journal Solid-State Circuits (Oct. 2004) 39 (1680-1689)) , 2004 .
[17] Beomsup Kim,et al. A low-phase-noise CMOS LC oscillator with a ring structure , 2000 .
[18] S.P. Voinigescu,et al. 6-k/spl Omega/, 43-Gb/s differential transimpedance-limiting amplifier with auto-zero feedback and high dynamic range , 2003, 25th Annual Technical Digest 2003. IEEE Gallium Arsenide Integrated Circuit (GaAs IC) Symposium, 2003..
[19] G. Gonzalez. Microwave Transistor Amplifiers: Analysis and Design , 1984 .
[20] Kevin T. Kornegay,et al. SiGe Using a Low-Voltage Logic Family , 2005 .
[21] Behzad Razavi,et al. A 40 Gb/s clock and data recovery circuit in 0.18 μm CMOS technology , 2003 .
[22] K.T. Kornegay,et al. Jitter considerations in the design of a 10-Gb/s automatic gain control amplifier , 2005, IEEE Transactions on Microwave Theory and Techniques.
[23] H. Shigematsu,et al. 4 40 Gb / s CMOS Distributed Amplifier for Fiber-Optic Communication Systems , 2001 .
[24] M. Rodwell,et al. 40Gb/s CMOS distributed amplifier for fiber-optic communication systems , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).
[25] Jri Lee,et al. 11.3 A 7-Band 3-8GHz Frequency Synthesizer , 2005 .
[26] H. Nosaka,et al. A 39-to-45-Gbit/s multi-data-rate clock and data recovery circuit with a robust lock detector , 2004, IEEE Journal of Solid-State Circuits.
[27] A. Leven,et al. SiGe differential transimpedance amplifier with 50 GHz bandwidth , 2002, 24th Annual Technical Digest Gallium Arsenide Integrated Circuit (GaAs IC) Symposiu.
[28] Maurizio Salaris,et al. Low-mass stellar models with new opacity tables and varying α-element enhancement factors , 2006, Proceedings of the International Astronomical Union.
[29] Jun-De Jin,et al. 40-Gb/s Transimpedance Amplifier in 0.18-μm CMOS Technology , 2006, 2006 Proceedings of the 32nd European Solid-State Circuits Conference.
[30] J. Lee,et al. A 40 Gb/s clock and data recovery circuit in 0.18 /spl mu/m CMOS technology , 2003, 2003 IEEE International Solid-State Circuits Conference, 2003. Digest of Technical Papers. ISSCC..
[31] Sorin P. Voinigescu,et al. Correction to “6-k $Omega$ 43-Gb/s Differential Transimpedance-Limiting Amplifier With Auto-Zero Feedback and High Dynamic Range” , 2004 .
[32] M.L. Schmatz,et al. A 40-Gb/s, digitally programmable peaking limiting amplifier with 20-dB differential gain in 90-nm CMOS , 2006, IEEE Radio Frequency Integrated Circuits (RFIC) Symposium, 2006.