Reconfigurable Communication Networks in a Parametric SIMD Parallel System on Chip

The SIMD parallel systems play a crucial role in the field of intensive signal processing. For most the parallel systems, communication networks are considered as one of the challenges facing researchers. This work describes the FPGA implementation of two reconfigurable and flexible communication networks integrated into mppSoC. An mppSoC system is an SIMD massively parallel processing System on Chip designed for data-parallel applications. Its most distinguished features are its parameterization and the reconfigurability of its interconnection networks. This reconfigurability allows to establish one configuration with a network topology well mapped to the algorithm communication graph so that higher efficiency can be achieved. Experimental results for mppSoC with different communication configurations demonstrate the performance of the used reconfigurable networks and the effectiveness of algorithm mapping through reconfiguration.

[1]  Pankaj Kumar.  An Fpga Based Simd Architecture Implemented with 2d Systolic Architecture for Image Processing , 2006 .

[2]  R. Michael Hord,et al.  The Illiac IV, the first supercomputer , 1982 .

[3]  Behrooz Parhami,et al.  Introduction to Parallel Processing: Algorithms and Architectures , 1999 .

[4]  Hong Wang,et al.  Implementing a scalable ASC processor , 2003, Proceedings International Parallel and Distributed Processing Symposium.

[5]  W. Daniel Hillis,et al.  Data parallel algorithms , 1986, CACM.

[6]  Fadi J. Kurdahi,et al.  Design and Implementation of the MorphoSys Reconfigurable Computing Processor , 2000, J. VLSI Signal Process..

[7]  Dietmar Fey,et al.  A Programmable Parallel Processor Architecture in FPGAs for Image Processing Sensors , 2007 .

[8]  Michael J. Flynn,et al.  Some Computer Organizations and Their Effectiveness , 1972, IEEE Transactions on Computers.

[9]  Laurence T. Yang,et al.  Embedded and Ubiquitous Computing - EUC 2005, International Conference EUC 2005, Nagasaki, Japan, December 6-9, 2005, Proceedings , 2005, EUC.

[10]  Dominique Ginhac,et al.  An SIMD Programmable Vision Chip with High-Speed Focal Plane Image Processing , 2008, EURASIP J. Embed. Syst..

[11]  Sven E. Eklund,et al.  A Massively Parallel Architecture for Linear Machine Code Genetic Programming , 2001, ICES.

[12]  Sanyou Zeng,et al.  Evolvable Systems: From Biology to Hardware, 7th International Conference, ICES 2007, Wuhan, China, September 21-23, 2007, Proceedings , 2007, ICES.

[13]  Tae-Gyu Chang,et al.  An FPGA-Based Parallel Accelerator for Matrix Multiplications in the Newton-Raphson Method , 2005, EUC.

[14]  Henk Corporaal,et al.  RC-SIMD: Reconfigurable communication SIMD architecture for image processing applications , 2006, J. Embed. Comput..

[15]  Tom Blank,et al.  The MasPar MP-1 architecture , 1990, Digest of Papers Compcon Spring '90. Thirty-Fifth IEEE Computer Society International Conference on Intellectual Leverage.