1991 ACM/SIGDA International Workshop on Formal Methods in VLSI Design

The workshop was designed to meet the increased interest, both in academia and industry, in the aplication of formal methods to the design of reliable, testable, and robust integrated systems. Previous workshops in this series (organized within the scope of IFIP WG 10.2 and and WG 10.5) have been held in Europe. This is the first workshop of its nature that has been sponsored by SIGDA and held in the U.S.A. The emphasis of this year's meeting was to provide an opportunity for synergistic interaction between researchers in "traditional" CAD and those interested in formal approaches to design. The workshop was truly international in flavour, with a significant percentage of non-US participants, including Europe and some from Asia and Japan. The number of registrants was planned between 50-75 in order to foster open discussion among the participants. The official list of participants lists 77 registrants to the workshop. The workshop organization sought to promote interaction by interleaving frequent discussion breaks into the technical program, scheduling three panel discussions that included general (audience) discussions, and a wrap up discussion panel entitled "What have we learned, and where do we go from here?" that solicited input from all of the session chairs (and indirectly from their session participants). This strategy proved to be very successful in engendering several lively technical exchanges. Technical P r o g r a m The program committee accepted 33 papers for presentation and 14 papers for poster sessions. The papers covered a wide spectrum of research in formal methods, ranging from verification, timing, synthesis, and specification; some discussion on testing as it related to the other topics was also featured. A significant number of the papers submitted were related to techniques for formal verification, underlining the increased interest in this topic in the design community. In the area of verification, it was apparent that combinational and finite state machine verification strategies had progressed rapidly to the point where they are having an impact on CAD tool suites. Significant examples were also being attempted with other more general techniques, and a smooth integration with existing hardware description languages was becoming an issue (particularly in that no existing commercial HDL was deemed very appropriate for verification). There was debate about the appropriate levels of models that were appropriate for timing description. Another emerging theme was that synthesis systems were 70 SIGDA Newsletter, vol 21, number I being modified to …