BTI variability fundamental understandings and impact on digital logic by the use of extensive dataset

This paper presents understandings on BTI variability based upon an extensive dataset. This enables to select between various theoretical statistical models and to propose a novel description approach for the NBTI-induced mismatch for different technological nodes and a comparison with time-zero variability. The impact from transistor to gate level is also evaluated.

[1]  O. Rozeau,et al.  28nm FDSOI technology platform for high-speed low-voltage digital applications , 2012, 2012 Symposium on VLSI Technology (VLSIT).

[2]  N. Horiguchi,et al.  Impact of single charged gate oxide defects on the performance and scaling of nanoscaled FETs , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[3]  X. Federspiel,et al.  Bias temperature instability and hot carrier circuit ageing simulations specificities in UTBB FDSOI 28nm node , 2013, 2013 IEEE International Reliability Physics Symposium (IRPS).

[4]  S. Rauch The statistics of NBTI-induced V/sub T/ and /spl beta/ mismatch shifts in pMOSFETs , 2002 .

[5]  M. Rafik,et al.  28nm node bulk vs FDSOI reliability comparison , 2012, 2012 IEEE International Reliability Physics Symposium (IRPS).

[6]  S. Rauch,et al.  Review and Reexamination of Reliability Effects Related to NBTI-Induced Statistical Variations , 2007, IEEE Transactions on Device and Materials Reliability.

[7]  V. Huard,et al.  NBTI degradation: From transistor to SRAM arrays , 2008, 2008 IEEE International Reliability Physics Symposium.

[8]  R. Degraeve,et al.  Origin of NBTI variability in deeply scaled pFETs , 2010, 2010 IEEE International Reliability Physics Symposium.

[9]  B. Kaczer,et al.  Degradation of time dependent variability due to interface state generation , 2013, 2013 Symposium on VLSI Technology.