Cascaded Channel Model and Analysis for STT-MRAM

Spin-torque transfer magnetic random access memory (STTMRAM) is a promising emerging non-volatile memory (NVM) technology which shows high potential for replacing the dynamic random access memory (DRAM), as well as for various embedded applications. However, STT-MRAM suffers from process variation induced variations of the access transistor size, the magnetic tunneling junction (MTJ) geometry and resistance, as well as random thermal fluctuations [1], leading to the write error, the read disturb error, and the read decision error. Therefore, advanced channel coding and signal processing techniques are expected to improve system’s reliability in the presence of both write errors and read errors. Channel modeling is the prerequisite for the design of channel codes and detectors. In the literature, many works have been done to model the MTJ based on transport physics and magnetization dynamics [2]. Other works have also been reported which model the STT-MRAM cell from circuit and system perspective including the compact models [3]. However, none of the above models can be considered as a communication type channel model. Moreover, they are all too slow to support the error rate simulations of the STT-MRAM array. In this work [4], we first propose a novel cascaded channel model, which incorporates both the write errors and read errors for STT-MRAM. We then derive analytically the channel raw bit error rate (BER), based on which we obtain the optimum hard memory sensing threshold. We further derive the bit log-likelihood-ratio (LLR) which enables soft-decision decoding (SDD) of error correction codes (ECCs). We also derive the maximum likelihood (ML) decision criterion for the cascaded channel. These theoretical works serve as basis for the design of advanced channel coding schemes for STTMRAM. We finally present a hybrid decoding algorithm for extended Hamming codes for STT-MRAM, to illustrate the application of the proposed channel model and its analysis.

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[2]  Mircea R. Stan,et al.  Advances and Future Prospects of Spin-Transfer Torque Random Access Memory , 2010, IEEE Transactions on Magnetics.

[3]  Yiran Chen,et al.  STT-RAM cell design optimization for persistent and non-persistent error rate reduction: A statistical design view , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[4]  Yiran Chen,et al.  Asymmetry of MTJ switching and its implication to STT-RAM designs , 2012, 2012 Design, Automation & Test in Europe Conference & Exhibition (DATE).

[5]  K. Cai,et al.  A cascaded channel model and hybrid decoding for spin-torque transfer magnetic random access memory (STT-MRAM) , 2017, 2017 IEEE International Magnetics Conference (INTERMAG).