Low-power equalizers for 51.84 Mb/s very-high-speed digital subscriber loop (VDSL) modems

We present low-power equalizers derived via dynamic algorithm transformations (DAT). These transformations achieve low-energy operation by reconfiguring the architecture and the supply voltage in response to channel non-stationarities. Practical reconfiguration strategies are derived as a solution to an optimization problem with energy as the objective function and a constraint on the algorithm performance (specifically the SNR). Simple energy models for multipliers are presented. The DAT-based adaptive filter is employed as an equalizer for 51.84 Mbit/s very high-speed digital subscriber loop (VDSL) over 24-pair BKMA cable. On average, 88% energy savings are achieved due to variations in cable length and number of far-end crosstalk (FEXT) interferers.

[1]  Anantha Chandrakasan,et al.  Embedded power supply for low-power DSP , 1997, IEEE Trans. Very Large Scale Integr. Syst..

[2]  Naresh R. Shanbhag,et al.  VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access , 1998, IEEE Trans. Signal Process..

[3]  K. Azadet,et al.  A low power 128-tap digital adaptive equalizer for broadband modems , 1997, 1997 IEEE International Solids-State Circuits Conference. Digest of Technical Papers.

[4]  Miodrag Potkonjak,et al.  Optimizing power using transformations , 1995, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[5]  T.H. Meng,et al.  A low-power video-rate pyramid VQ decoder , 1996, 1996 IEEE International Solid-State Circuits Conference. Digest of TEchnical Papers, ISSCC.

[6]  Naresh R. Shanbhag,et al.  Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN , 1997, IEEE Trans. Signal Process..

[7]  V. K. Madisetti,et al.  LMSGEN: a prototyping environment for programmable adaptive digital filters in VLSI , 1994, Proceedings of 1994 IEEE Workshop on VLSI Signal Processing.

[8]  Anantha P. Chandrakasan,et al.  Low-power digital filtering using approximate processing , 1996 .

[9]  Naresh R. Shanbhag,et al.  Dynamic algorithm transformations (DAT) for low-power adaptive signal processing , 1997, Proceedings of 1997 International Symposium on Low Power Electronics and Design.

[10]  Keshab K. Parhi,et al.  Low-Area/Power Parallel FIR Digital Filter Implementations , 1997, J. VLSI Signal Process..