RTL level preparation of high-quality/low-energy/low-power BIST

While high-quality BIST (built-in self test) based on deterministic vectors often has a prohibitive cost, pseudorandom based BIST may lead to low DC (defect coverage) values, requiring however very long test sequences with the corresponding energy waste and possible overheating due to extra switching activity caused by test vectors. The purpose of this paper is to discuss how a recently proposed RTL (register transfer level) test preparation methodology can be reused to drive innovative, high-quality/low-energy/low-power BIST solutions. RTL test generation is carried out through the definition of partially defined test vectors (masks) that, while targeting multiple detection of RTL faults lead to high DC values. An energy/power model is proposed to optimize the energy/power consumption of the test at RTL level. It is shown that the proposed method achieves better DC values with low-energy and low-power consumption, when compared to pseudo-random test excitation. The usefulness of the methodology is ascertained using the VERIDOS simulation environment in modules of the CMUDSP and TORCH ITC'99 benchmark circuits.

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