Parametric distribution and feature level analysis of different types of gated resistors

Gated resistor is an accumulation mode device without any junction (p-n junction or Schottky junction) in which the channel doping concentration is generally equal to doping concentration on the source and drain. Gated resistors have been fabricated to avoid the super steep and troublesome doping profile of conventional Metal Oxide Semiconductor Field Effect Transistor (MOSFET). It simplifies the current-flow due to the elimination of Semiconductor/Insulator interface to a great extent. The advantage of gated resistor includes the avoidance of the junction by which the process flow and architecture are highly simplified. Its self alignment behavior avoids the thermal budget needed for dopant activation after gate stack formation. Ultrathin device layer of very highly doped semiconductor is present in this device. Here we have analyzed different types of gated resistors, their architectures, characteristics, pros and cons. Different types of gated resistors included here are Multiple Independent Gate Field Effect Transistor (MIGFET) having more than one gate independent of each other, Junction-Less Tunnel Field Effect Transistor (JL-TFET) where tunneling effect occurs, Bulk Planar (BP) Gated Resistor forming over the bulk silicon, Silicon On Insulator (SOI) Gated Resistor in the presence of spacer and Vertical Slit Field Effect Transistor (VeSFET) where vertical silicon channel and metal pillar are present.

[1]  Junctionless Ge p-Channel Metal-Oxide-Semiconductor Field-Effect Transistors Fabricated on Ultrathin Ge-on-Insulator Substrate , 2011 .

[2]  Chenming Hu.  SOI and nanoscale MOSFETs , 2001, Device Research Conference. Conference Digest (Cat. No.01TH8561).

[3]  Yongtaek Hong,et al.  DEVICE RESEARCH CONFERENCE , 2011 .

[4]  Behzad Razavi,et al.  RF Microelectronics , 1997 .

[5]  H. Grubin.  The physics of semiconductor devices , 1979, IEEE Journal of Quantum Electronics.

[6]  G.E. Moore,et al.  Cramming More Components Onto Integrated Circuits , 1998, Proceedings of the IEEE.

[7]  R. Yu.  A study of silicon and germanium junctionless transistors , 2013 .

[8]  S. Ganguly,et al.  Effect of Band-to-Band Tunneling on Junctionless Transistors , 2012, IEEE Transactions on Electron Devices.

[9]  G. A. Armstrong,et al.  High-Performance Junctionless MOSFETs for Ultralow-Power Analog/RF Applications , 2012, IEEE Electron Device Letters.

[10]  Chi-Woo Lee,et al.  Junctionless multigate field-effect transistor , 2009 .

[11]  Jean-Pierre Colinge,et al.  Junctionless transistors , 2012, IMFEDK 2012.

[12]  M. J. Deen,et al.  Electrical characteristics of 20-nm junctionless Si nanowire transistors , 2012 .

[13]  P. Mondal,et al.  Hetero-gate-dielectric double gate junctionless transistor (HGJLT) with reduced band-to-band tunnelling effects in subthreshold regime , 2014 .

[14]  J R A Beale,et al.  Solid State Electronic Devices , 1973 .

[15]  Strain Sensitivity of MOSFET Devices , 1977, IEEE Transactions on Instrumentation and Measurement.