Analysis and comparison of WLCSP‐on‐build‐up PCB assemblies with various solders and microvia configurations

In this paper, a computational analysis is presented for the comparison of wafer level chip scale package‐on‐build‐up PCB assemblies with various solders and microvia configurations. The printed circuit board of the assembly has one build‐up layer on one side. For comparison, the board with two build‐up layers on the same side is studied as well. Furthermore, two solder joint materials, namely, 62Sn–2Ag–36Pb and 96.5Sn–3.5Ag are studied for comparison. The assembly is simulated by a finite element model and the model is analyzed under thermal cyclic loading. A comprehensive stress analysis is performed and comparisons are made for assembly deformation, stress/strain ranges, and creep responses.

[1]  J. Lau,et al.  Creep behaviors of flip chip on board with 96.5Sn-3.5Ag and 100In lead-free solder joints , 2000 .

[2]  John H. Lau,et al.  Solder joint crack propagation analysis of wafer-level chip scale package on printed circuit board assemblies , 2001 .

[3]  Recent advances on a wafer-level flip chip packaging process , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[4]  John H. Lau,et al.  Microvias: For Low Cost, High Density Interconnects , 2001 .

[5]  Sa-Yoon Kang,et al.  Optimal structure of wafer level package for the electrical performance , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[6]  Herbert Reichl,et al.  Board level reliability of a waferlevel CSP using stacked solder spheres and a solder support structure (S/sup 3/) , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[7]  John H. Lau,et al.  Nonlinear fracture mechanics analysis of wafer level chip scale package solder joints with cracks , 2000 .

[8]  J. H. Lau.  Critical issues of wafer level chip scale package (WLCSP) with emphasis on cost analysis and solder joint reliability , 2002 .

[9]  A.R. Mirza.  One micron precision, wafer-level aligned bonding for interconnect, MEMS and packaging applications , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[10]  Thomas Oppert,et al.  Wafer level CSP using low cost electroless redistribution layer , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[11]  J. Lau,et al.  Solder Joint Reliability of BGA, CSP, Flip Chip, and Fine Pitch SMT Assemblies , 1996 .

[12]  N. Kelkar,et al.  A manufacturing perspective of wafer level CSP , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[13]  K. Banerji,et al.  Constitutive relations for tin-based-solder joints , 1992, 1992 Proceedings 42nd Electronic Components & Technology Conference.

[14]  P. Garrou,et al.  Wafer level chip scale packaging (WL-CSP): an overview , 2000, ECTC 2000.

[15]  John H. Lau,et al.  An overview of microvia technology , 2000 .

[16]  H. Reichl,et al.  Fab Integrated Packaging (FIP): a new concept for high reliability wafer-level chip size packaging , 2000, 2000 Proceedings. 50th Electronic Components and Technology Conference (Cat. No.00CH37070).

[17]  D.C. O'Brien,et al.  Fabrication of wafer level chip scale packaging for optoelectronic devices , 1999, 1999 Proceedings. 49th Electronic Components and Technology Conference (Cat. No.99CH36299).