Approximation of wiring delay in MOSFET LSI

Two approximation methods for wiring delay in MOS LSI are studied. One is analytical and the other is a lumped circuit approximation. The basic model for wiring is a distributed CR line with a drive MOSFET at one end and a capacitive load at the other end. Simple approximated formulas for the delay and the step response of this model are obtained. Approximation of a distributed CR line by lumped Rs and C's combination, which is very useful when incorporated in circuit simulation programs, is also investigated. The widely used L ladder circuit model is found to be a poor approximation, while /spl pi/ and T ladder circuit models give satisfactory results. The simplest circuits that approximate the interconnection line within a given tolerant error are tabulated under various drive and load conditions.