Hot carrier degradation of lateral DMOS transistor capacitance and reliability issues

This paper reports on an experimental evaluation of the hot-carrier impact on capacitances of high voltage DMOS transistors and their correlation with the degradation of DC characteristics. Two stress conditions were selected: (i) stress-A: at maximum drain voltage (near breakdown) and a gate voltage providing maximum body-current, I/sub Bmax/, and; (ii) stress-B: at maximum drain and gate voltages, which are the most relevant for device reliability. The proposed investigations experimentally distinguish among drift-region degradation, for stress-A, and gate oxide degradation near the source-end, for stress-B. In the case of stress-B, while traditional DC evaluation of stress impact suggests a significant shift in the DC parameters, the DMOS AC characteristics appear considerably altered. This suggests the importance of the systematic experimental evaluation of the impact of hot-carrier degradation of AC characteristics and its correlation with DC degradation in order to explain the degradation mechanisms.

[1]  G. Groeseneken,et al.  Hot-carrier degradation phenomena in lateral and vertical DMOS transistors , 2004, IEEE Transactions on Electron Devices.

[2]  P. Moens,et al.  Competing hot carrier degradation mechanisms in lateral n-type DMOS transistors , 2003, 2003 IEEE International Reliability Physics Symposium Proceedings, 2003. 41st Annual..

[3]  R. Versari,et al.  Experimental study of hot-carrier effects in LDMOS transistors , 1999 .

[4]  T. Terashima Multi-voltage device integration technique for 0.5μm BiCMOS & DMOS process , 2000 .

[5]  Bruno Ricco,et al.  A new characterization method for hot-carrier degradation in DMOS transistors , 1998 .

[6]  C. Tsai,et al.  16-60 V rated LDMOS show advanced performance in a 0.72 /spl mu/m evolution BiCMOS power technology , 1997, International Electron Devices Meeting. IEDM Technical Digest.

[7]  Prasad Chaparala,et al.  Hot carrier reliability of N-LDMOS transistor arrays for power BiCMOS applications , 2002, 2002 IEEE International Reliability Physics Symposium. Proceedings. 40th Annual (Cat. No.02CH37320).

[8]  M. K. Alam,et al.  Arriving at a unified model for hot-carrier degradation in MOSFET's through gate-to-drain capacitance measurement , 1994 .

[9]  R. Degraeve,et al.  A novel hot-hole injection degradation model for lateral nDMOS transistors , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[10]  C.H. Ling,et al.  Observation of MOSFET degradation due to electrical stressing through gate-to-source and gate-to-drain capacitance measurement , 1991, IEEE Electron Device Letters.

[11]  N. Camilleri,et al.  Extracting small-signal model parameters of silicon MOSFET transistors , 1994, 1994 IEEE MTT-S International Microwave Symposium Digest (Cat. No.94CH3389-4).

[12]  D. Ang,et al.  A study of hot carrier degradation in NMOSEET's by gate capacitance and charge pumping current , 1995 .

[13]  T. Terashima,et al.  Multi-voltage device integration technique for 0.5 /spl mu/m BiCMOS and DMOS process , 2000, 12th International Symposium on Power Semiconductor Devices & ICs. Proceedings (Cat. No.00CH37094).