Transistor and pin reordering for gate oxide leakage reduction in dual T/sub ox/ circuits

Gate oxide tunneling current (I/sub gate/) is emerging as a key roadblock for device scaling in nanometer-scale CMOS circuits. A practical means to reduce I/sub gate/ is to leverage dual T/sub ox/ processes where non-critical transistors are assigned a thicker T/sub ox/. In this paper, we generate a leakage/delay tradeoff curve for dual T/sub ox/ circuits, and propose a transistor and pin reordering technique that has a minimal layout impact to further reduce the total leakage current up to 18% and I/sub gate/ up to 26% without incurring any delay penalty.

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