A 197mW 70ms-Latency Full-HD 12-Channel Video-Processing SoC in 16nm CMOS for In-Vehicle Information Systems

[1]  Chong-Min Kyung,et al.  A Lossless Embedded Compression Using Significant Bit Truncation for HD Video Coding , 2010, IEEE Transactions on Circuits and Systems for Video Technology.

[2]  Youn-Long Lin,et al.  A Hybrid Algorithm for Effective Lossless Compression of Video Display Frames , 2012, IEEE Transactions on Multimedia.

[3]  Satoshi Goto,et al.  Reducing power consumption of HEVC codec with lossless reference frame recompression , 2014, 2014 IEEE International Conference on Image Processing (ICIP).

[4]  Tsung-Han Tsai,et al.  An efficient embedded compression algorithm using adjusted binary code method , 2008, 2008 IEEE International Symposium on Circuits and Systems.

[5]  Liang-Gee Chen,et al.  Multimode Embedded Compression Codec Engine for Power-Aware Video Coding System , 2009, IEEE Transactions on Circuits and Systems for Video Technology.

[6]  Hyuk-Jae Lee,et al.  A New Frame Recompression Algorithm Integrated with H.264 Video Compression , 2007, 2007 IEEE International Symposium on Circuits and Systems.

[7]  Anantha Chandrakasan,et al.  A 249Mpixel/s HEVC video-decoder chip for Quad Full HD applications , 2013, 2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers.

[8]  Y.V. Ivanov,et al.  Reference Frame Compression Using Embedded Reconstruction Patterns for H.264/AVC Decoder , 2008, 2008 The Third International Conference on Digital Telecommunications (icdt 2008).

[9]  Tian Song,et al.  Reference frame data compression method for H.264/AVC , 2007, IEICE Electron. Express.

[10]  Chao-Chyun Chen,et al.  Design of VLSI Architecture of Autocorrelation-Based Lossless Recompression Engine for Memory-Efficient Video Coding Systems , 2013, Circuits, Systems, and Signal Processing.

[11]  Keiji Matsumoto,et al.  A 342mW mobile application processor with full-HD multi-standard video codec , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.

[12]  Makoto Takahashi,et al.  A 222mW H.264 Full-HD decoding application processor with x512b stacked DRAM in 40nm , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[13]  Hoon Yoo,et al.  A low complexity and lossless frame memory compression for display devices , 2008, IEEE Transactions on Consumer Electronics.

[14]  Satoshi Goto,et al.  Lossless embedded compression using multi-mode DPCM & averaging prediction for HEVC-like video codec , 2013, 21st European Signal Processing Conference (EUSIPCO 2013).

[15]  Toshihiro Hattori,et al.  4.4 A 197mW 70ms-latency full-HD 12-channel video-processing SoC for car information systems , 2016, 2016 IEEE International Solid-State Circuits Conference (ISSCC).

[16]  Young-Min Kim,et al.  Low complexity embedded compression algorithm for reduction of memory size and bandwidth requirements in the JPEG2000 encoder , 2010, IEEE Transactions on Consumer Electronics.