QoS architecture and design process for cost effective Network on Chip

buffers and links that support these four classes. This generic architecture is subsequently optimized to minimize cost (area and power) while maintaining the required QoS. The network architecture is based on the following principles: The network topology is a planar grid of switches that route the traffic according to fixed shortest path (X-Y based) discipline, thus minimizing hardware tables and traffic overheads. Buffer requirements are reduced by employing multi-class wormhole forwarding while allowing inter-class priorities. The layout of the network is customized and bandwidth is allocated to links according to their relative load so that the utilization of links in the network is balanced. During customization unnecessary resources (links, routers, buffers) are trimmed where possible, resulting in a low cost customized layout for the specific SoC. Analytic calculations and traffic simulations are used in the optimization steps to ensure that QoS is strictly met. I. INTRODUCTION On-chip packet-switched networks [1]-[11] have been proposed as a solution for the problem of global interconnect in deep sub-micron VLSI Systems-on-Chip (SoC). Networks on Chip (NoC) can address and contain major physical issues such as synchronization, noise, error-correction and speed optimization. NoC can also improve design productivity by supporting modularity and reuse of complex cores, thus enabling a higher level of abstraction in architectural modeling of future systems [4], [5]. However, VLSI designers must be ensured that the benefits of NoC do not compromise system performance and cost [8], [10]. Performance concerns are associated with latency and throughput. Cost concerns are primarily chip-area and power dissipation. This paper presents a design process and a network architecture that satisfy Quality of Service (performance) requirements at a measurable cost which is favorably compared with alternative on-chip interconnection approaches.