Recent advances in in-situ and in-field aging monitoring and compensation for integrated circuits: Invited paper

This paper reviews recent advances in in-situ and in-field techniques for monitoring and compensating aging in digital integrated circuits. For pipelines, we introduce an approach that combines circuit reconfiguration and voltage scaling down to so-called zero temperature coefficient voltage. This can directly monitor the delays of critical paths robustly against temperature variation. For SRAM circuits, we introduce new column and row peripheral circuits that can in-situ sense threshold voltage of each of six transistors in every bitcell, accurately against temperature variation in field post system deployment. We also introduce a software framework that can extract microarchitecture/circuit-level information from sensing results. With these techniques, we can exercise aging compensation schemes that can pin-point the components that undergo the worst-case aging effects. These monitoring and compensation techniques can contribute to the implementation of in-field reliability management. With such scheme a chip periodically and opportunistically enters a maintenance session. This enables each chip achieve near-optimal performance and energy-efficiency under a reliability envelope without imposing the design-time worst-case margin.

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