New Efficient 2T and Gate Design

This paper proposes a new design of 2T AND gate. Performance comparison of proposed gate with existing 2T GDI technique is presented. Different methods have been compared with respect to the number of devices, power consumption, power-delay product, temperature sustainability and noise immunity in order to prove the superiority of proposed design over existing 2T gate design. The simulation has been carried out on Tanner EDA tool on BSIM3v3 90nm technology.

[1]  Po-Ming Lee,et al.  Novel 10-T full adders realized by GDI structure , 2007, 2007 International Symposium on Integrated Circuits.

[2]  John P. Uyemura,et al.  Circuit design for CMOS VLSI , 1992 .

[3]  Israel A. Wagner,et al.  Gate-diffusion input (GDI): a power-efficient method for digital combinatorial circuits , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[4]  Anura P. Jayasumana,et al.  Pass-transistor logic design , 1991 .

[5]  Yasuhiko Sasaki,et al.  Top-down pass-transistor logic design , 1996, IEEE J. Solid State Circuits.

[6]  Yintang Yang,et al.  Novel low power full adder cells in 180nm CMOS technology , 2009, 2009 4th IEEE Conference on Industrial Electronics and Applications.

[7]  Anantha P. Chandrakasan,et al.  Low-power CMOS digital design , 1992 .

[8]  M.B. Srinivas,et al.  New improved 1-bit full adder cells , 2008, 2008 Canadian Conference on Electrical and Computer Engineering.

[9]  Mohamed I. Elmasry,et al.  Circuit techniques for CMOS low-power high-performance multipliers , 1996 .

[10]  Wolfgang Fichtner,et al.  Low-power logic styles: CMOS versus pass-transistor logic , 1997, IEEE J. Solid State Circuits.