An implementation of high-speed decoder for double-error-correcting binary BCH codes in programmable logic array chip
暂无分享,去创建一个
[1] James L. Massey,et al. Step-by-step decoding of the Bose-Chaudhuri- Hocquenghem codes , 1965, IEEE Trans. Inf. Theory.
[2] Hideki Imai,et al. A Construction Method of High-Speed Decoders Using ROM's for Bose–Chaudhuri–Hocquenghem and Reed–Solomon Codes , 1987, IEEE Transactions on Computers.
[3] James L. Massey,et al. Review of 'Error-Correcting Codes, 2nd edn.' (Peterson, W. W., and Weldon, E. J., Jr.; 1972) , 1973, IEEE Trans. Inf. Theory.
[4] Shyue-Win Wei,et al. High-speed hardware decoder for double-error-correcting binary BCH codes , 1989 .
[5] T. Miki,et al. Error correction capabilities of BCH codes with interleaving in Rayleigh fading channel , 1988 .