Zero temperature-coefficient bias point over wide range of temperatures for single- and double-gate UTB-SOI n-MOSFETs with trapped charges

Abstract This paper is a unique attempt to identify the zero-temperature-coefficient ( ZTC ) point and other performance metrics for single gate (SG), double gate (DG), and gate stack double gate (GS-DG), ultra-thin body (UTB) silicon on insulator (SOI) n-MOSFET over wide range of temperatures (100–400 K) through 2-D device simulation. During the pre- and post-fabrication process, availability of the trapped charges is quite common and cannot be neglected in nanoscale devices. Subsequently the effect has been considered in simulation. Simulation results show the existence of a biasing point i.e. ZTC bias point, where the device parameters become independent of temperature. The impact of operating temperature ( T ) on various performance metrics like on current ( I on ), off current ( I off ), on-off current ratio ( I on /I off ), transconductance ( g m ), output conductance ( g d ), intrinsic gain ( A V ) and cut off frequency ( f T ) is also subjected to extensive analysis. The variation of ZTC point for transconductance ( Z T C g m ) and drain current ( Z T C I D S ) from SG to DG and GS-DG is compared. This further validates the application opportunities involved in designing RF circuits for a wide range of temperature applications.

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