Distortion in RF CMOS short-channel low-noise amplifiers

An approach to estimate the distortion in CMOS short-channel (e.g. 0.18-/spl mu/m gate length) RF low-noise amplifiers (LNAs), based on Volterra's series, is presented. Compact and accurate frequency-dependent closed-form expressions describing the effects of the different transistor parameters on harmonic distortion are derived. For the first time, the second-order distortion (HD2), in CMOS short-channel based LNAs, is studied. This is crucial for systems such as homodyne receivers. Equations describing third-order intermodulation distortion in RF LNAs are reported. The analytical analysis is verified through simulations and measured results of an 0.18-/spl mu/m CMOS 5.8-GHz folded-cascode LNA prototype chip geared toward sub-1-V operation. It is shown that the distortion is independent of the gate-source capacitance C/sub gs/ of the MOS transistors, allowing an extra degree of freedom in the design of LNA circuits. Distortion-aware design guidelines for RF CMOS LNAs are provided throughout the paper.

[1]  Calvin Plett,et al.  RF circuit implications of moderate inversion enhanced linear region in MOSFETs , 2004, IEEE Transactions on Circuits and Systems I: Regular Papers.

[2]  P. Sen,et al.  Reconfigurable RFICs in Si-based technologies for a compact intelligent RF front-end , 2005, IEEE Transactions on Microwave Theory and Techniques.

[3]  Xiang Guan,et al.  A 24-GHz CMOS front-end , 2004, IEEE Journal of Solid-State Circuits.

[4]  Sorin P. Voinigescu,et al.  5 GHz SiGe HBT monolithic radio transceiver with tunable filtering , 1999, 1999 IEEE Radio Frequency Integrated Circuits Symposium (Cat No.99CH37001).

[5]  Mourad N. El-Gamal,et al.  Distortion analysis of high-frequency log-domain filters using Volterra series , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[6]  Kwyro Lee,et al.  Highly linear receiver front-end adopting MOSFET transconductance linearization by multiple gated transistors , 2004, IEEE Journal of Solid-State Circuits.

[7]  Mourad N. El-Gamal,et al.  Gain and frequency controllable sub-1 V 5.8 GHz CMOS LNA , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[8]  Edgar Sanchez-Sinencio,et al.  A 2.7-V 1.8-GHz fourth-order tunable LC bandpass filter based on emulation of magnetically coupled resonators , 2003, IEEE J. Solid State Circuits.

[9]  Mourad N. El-Gamal,et al.  Distortion in RF CMOS short channel low noise amplifiers , 2005 .

[10]  Bumman Kim,et al.  Linearity analysis of CMOS for RF application , 2002, IMS 2002.

[11]  Wouter A. Serdijn,et al.  Optimal distribution of the RF front-end system specifications to the RF front-end circuit blocks , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[12]  Y. Deval,et al.  A 0.9V body effect feedback 2 GHz low noise amplifier , 2003, ESSCIRC 2004 - 29th European Solid-State Circuits Conference (IEEE Cat. No.03EX705).

[13]  Calvin Plett,et al.  A 5 GHz radio front-end with automatically Q tuned notch filter , 2002, Proceedings of the Bipolar/BiCMOS Circuits and Technology Meeting.

[14]  R.G. Meyer,et al.  Intermodulation distortion in current-commutating CMOS mixers , 2000, IEEE Journal of Solid-State Circuits.

[15]  D.K. Ma,et al.  A 17.1-17.3-GHz image-reject downconverter with phase-tunable LO using 3/spl times/ subharmonic injection locking , 2004, IEEE Journal of Solid-State Circuits.

[16]  A.F.M. Anwar,et al.  Nonlinear analysis of GaN MESFETs with Volterra series using large-signal models including trapping effects , 2002 .

[17]  F. Svelto,et al.  A fully integrated 0.18-/spl mu/m CMOS direct conversion receiver front-end with on-chip LO for UMTS , 2004, IEEE Journal of Solid-State Circuits.

[18]  Chung-Yu Wu,et al.  A 5-GHz CMOS double-quadrature receiver front-end with single-stage quadrature generator , 2004, IEEE Journal of Solid-State Circuits.

[19]  Mourad N. El-Gamal,et al.  Very low-voltage (0.8V) CMOS receiver frontend for 5 GHz RF applications , 2002 .

[20]  C. Plett,et al.  A completely integrated 1.8 volt 5 GHz tunable image reject notch filter , 2001, 2001 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium (IEEE Cat. No.01CH37173).

[21]  Bumman Kim,et al.  Analysis of nonlinear behavior of power HBTs , 2002 .

[22]  Chang-Hoon Choi,et al.  Impact of poly-gate depletion on MOS RF linearity , 2003, IEEE Electron Device Letters.

[23]  B.A. Bloechel,et al.  64 GHz and 100 GHz VCOs in 90 nm CMOS using optimum pumping method , 2004, 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No.04CH37519).

[24]  R. Meyer,et al.  High-frequency nonlinearity analysis of common-emitter and differential-pair transconductance stages , 1998, IEEE J. Solid State Circuits.

[25]  Timo Rahkonen,et al.  Analysis of third-order intermodulation distortion in common-emitter BJT and HBT amplifiers , 2003, IEEE Trans. Circuits Syst. II Express Briefs.

[26]  Adiseno,et al.  A wide-band RF front-end for multiband multistandard high-linearity low-IF wireless receivers , 2002, IEEE J. Solid State Circuits.

[27]  D.B.M. Klaassen,et al.  RF-distortion in deep-submicron CMOS technologies , 2000, International Electron Devices Meeting 2000. Technical Digest. IEDM (Cat. No.00CH37138).

[28]  O. Rozeau,et al.  90nm SOI-CMOS of 150GHz f/sub max/ and 0.8dB NF/sub min/ @6GHz for SOC , 2002, 2002 IEEE International SOI Conference.

[29]  Janne Aikio,et al.  A 5th order Volterra study of a 30W LDMOS power amplifier , 2003, Proceedings of the 2003 International Symposium on Circuits and Systems, 2003. ISCAS '03..

[30]  Igor M. Filanovsky.  On design of narrow-band low-noise amplifiers with inductive source degeneration , 2000, Proceedings of the 43rd IEEE Midwest Symposium on Circuits and Systems (Cat.No.CH37144).

[31]  Hannu Tenhunen,et al.  Performance analysis of sampling switches in voltage and frequency domains using Volterra series , 2004, 2004 IEEE International Symposium on Circuits and Systems (IEEE Cat. No.04CH37512).

[32]  Mourad N. El-Gamal,et al.  A very low-voltage (0.8 V) CMOS receiver frontend for 5 GHz RF applications , 2002, 2002 IEEE International Symposium on Circuits and Systems. Proceedings (Cat. No.02CH37353).

[33]  H. Samavati,et al.  5-GHz CMOS wireless LANs , 2002 .

[34]  H. Zirath,et al.  A comprehensive analysis of IMD behavior in RF CMOS power amplifiers , 2004, IEEE Journal of Solid-State Circuits.

[35]  M. Hargrove,et al.  RF potential of a 0.18-/spl mu/m CMOS logic device technology , 2000 .

[36]  Mohammed Ismail,et al.  Analysis of nonlinearities in RF CMOS amplifiers , 1999, ICECS'99. Proceedings of ICECS '99. 6th IEEE International Conference on Electronics, Circuits and Systems (Cat. No.99EX357).

[37]  L. Larson,et al.  Modified derivative superposition method for linearizing FET low-noise amplifiers , 2004, IEEE Transactions on Microwave Theory and Techniques.

[38]  Peter R. Kinget,et al.  High-Frequency Distortion Analysis of Analog Integrated Circuits , 1999 .

[39]  S. A. Maas.  FET MODELS FOR VOLTERRA-SERIES ANALYSIS , 1999 .

[40]  Chien-Chang Huang,et al.  Analysis of microwave MESFET power amplifiers for digital wireless communications systems , 2004, IEEE Transactions on Microwave Theory and Techniques.

[41]  M. Hargrove,et al.  RF Potential of a 0 . 18-m CMOS Logic Device Technology , 2000 .

[42]  Marc Engels,et al.  Compact modeling of nonlinear distortion in analog communication circuits , 2000, DATE '00.