All-Digital Background Calibration Technique for Offset, Gain and Timing Mismatches in Time-Interleaved ADCs

This paper presents a method for all-digital background calibration of multiple channel mismatches including offset, gain and timing mismatches in time-interleaved analog to digital converters (TIADCs). The averaging technique is used to remove the offset mismatch at each channel. The gain mismatch is calibrated by calculating the power ratio of the subADC over the reference ADC. Timing skew is compensated by using Hadamard transform for error correction and least mean squares (LMS) algorithm for estimation of the clock skew. The performance improvement of TIADCs employing these techniques is demonstrated through numerical simulations.

[1]  Christian Vogel,et al.  The impact of combined channel mismatch effects in time-interleaved ADCs , 2005, IEEE Transactions on Instrumentation and Measurement.

[2]  Duc Minh Nguyen,et al.  All-Digital Calibration of Timing Skews for TIADCs Using the Polyphase Decomposition , 2016, IEEE Transactions on Circuits and Systems II: Express Briefs.

[3]  Behzad Razavi,et al.  Design Considerations for Interleaved ADCs , 2013, IEEE Journal of Solid-State Circuits.

[4]  Jean-François Naviner,et al.  Mixed-Signal Clock-Skew Calibration Technique for Time-Interleaved ADCs , 2008, IEEE Transactions on Circuits and Systems I: Regular Papers.

[5]  W. Black,et al.  Time interleaved converter arrays , 1980, 1980 IEEE International Solid-State Circuits Conference. Digest of Technical Papers.

[6]  Jie Zhou,et al.  All-Digital Blind Background Calibration Technique for Any Channel Time-Interleaved ADC , 2018, IEEE Transactions on Circuits and Systems I: Regular Papers.

[7]  Francesco Centurelli,et al.  Efficient Digital Background Calibration of Time-Interleaved Pipeline Analog-to-Digital Converters , 2012, IEEE Transactions on Circuits and Systems I: Regular Papers.

[8]  Duc Minh Nguyen,et al.  Hardware implementation of all digital calibration for undersampling TIADCs , 2015, 2015 IEEE International Symposium on Circuits and Systems (ISCAS).

[9]  P.J. Hurst,et al.  A 10b 120MSample/s time-interleaved analog-to-digital converter with digital background calibration , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[10]  Claudio Nani,et al.  A 480mW 2.6GS/s 10b 65nm CMOS time-interleaved ADC with 48.5dB SNDR up to Nyquist , 2011, 2011 IEEE International Solid-State Circuits Conference.

[11]  Christian Vogel,et al.  Adaptive blind compensation of gain and timing mismatches in M-channel time-interleaved ADCs , 2008, 2008 15th IEEE International Conference on Electronics, Circuits and Systems.

[12]  Kenneth W. Martin,et al.  A Sample-Time Error Compensation Technique for Time-Interleaved ADC Systems , 2007, 2007 IEEE Custom Integrated Circuits Conference.

[13]  Haruo Kobayashi,et al.  Explicit analysis of channel mismatch effects in time-interleaved ADC systems , 2001 .

[14]  A.H.M. van Roermund,et al.  Analog calibration of channel mismatches in time-interleaved ADCs , 2009 .

[15]  Van-Phuc Hoang,et al.  Background Calibration of Multiple Channel Mismatches in Time-Interleaved ADCs , 2019, 2019 3rd International Conference on Recent Advances in Signal Processing, Telecommunications & Computing (SigTelCom).

[16]  E. Iroaga,et al.  A background correction technique for timing errors in time-interleaved analog-to-digital converters , 2005, 2005 IEEE International Symposium on Circuits and Systems.

[17]  Shahzad Saleem,et al.  On Blind Identification of Gain and Timing Mismatches in T ime-Interleaved Analog-to-Digital Converters , 2010 .

[18]  Van-Phuc Hoang,et al.  Fully Digital Background Calibration Technique for Channel Mismatches in TIADCs , 2018, 2018 5th NAFOSTED Conference on Information and Computer Science (NICS).

[19]  Han Le Duc,et al.  A fully digital background calibration of timing skew in undersampling TI-ADC , 2014, 2014 IEEE 12th International New Circuits and Systems Conference (NEWCAS).

[20]  Masanori Furuta,et al.  All-Digital Background Calibration Technique for Time-Interleaved ADC Using Pseudo Aliasing Signal , 2013, IEEE Transactions on Circuits and Systems I: Regular Papers.