Exploiting Hybrid SPM-Cache Architectures to Reduce Energy Consumption for Embedded Computing

Scratch-Pad Memories (SPMs) have been increasingly used in embedded systems due to their time predictability and better energy efficiency as compared to caches. However, the SPM is typically controlled by software, which is less adaptive to runtime instruction/data access patterns that are dependent on the input data and hence may lead to performance degradation. In this paper, we study the energy dissipation of a number of hybrid on-chip memory architectures by combining both caches and SPMs without increasing the total on-chip memory size. In the hybrid SPM-cache architectures, the instructions/data in the SPMs can be accessed more energy-efficiently, while other instructions/data not stored into the SPMs can exploit the cache to take advantage of runtime locality for reducing energy consumption. Our experimental results indicate that with the equivalent total on-chip memory size, several hybrid SPM-cache architectures are more energy-efficient than either pure software-controlled SPMs or pure hardware-controlled caches. In particular, using the hybrid SPM-cache to store both instructions and data can achieve the best energy efficiency.