Design and Implementation of a Gigabit Ethernet TAP Card

The design and implementation of a Gigabit Ethernet TAP card is described.Using this TAP card,the frames of Gigabit Ethernet can be replicated and output to the TAP ports.In these frames accurate time stamps can be inserted.FPGA is used to implement these functions.The Nios II of the Altera FPGA is used to maintain the time synchronization with GPS.Because of the protection circuit,the monitored link can work well even the TAP card is powerdown.This TAP card can be used in the maintenance and detection of the soft switch and 3G networks.