Parallel Turbo decoding

Turbo codes are one of the most powerful error correcting codes. The VLSI implementation of Turbo codes for higher decoding speed requires use of parallel architectures. This paper explores the design spaces of both serial and parallel MAP decoders using graphical analysis. Several existing designs are compared, and three new parallel decoding schemes are presented.

[1]  William E. Ryan,et al.  Concatenated Convolutional Codes and Iterative Decoding , 2003 .

[2]  Francky Catthoor,et al.  Memory optimization of MAP turbo decoder algorithms , 2001, IEEE Trans. Very Large Scale Integr. Syst..

[3]  Keshab K. Parhi,et al.  High-performance, low-complexity vlsi design in turbo decoders , 2000 .

[4]  Keshab K. Parhi,et al.  Area-efficient high-speed decoding schemes for turbo decoders , 2002, IEEE Trans. Very Large Scale Integr. Syst..

[5]  Alain Glavieux,et al.  Reflections on the Prize Paper : "Near optimum error-correcting coding and decoding: turbo codes" , 1998 .

[6]  Norbert Wehn,et al.  A Scalable System Architecture for High-Throughput Turbo-Decoders , 2005, J. VLSI Signal Process..

[7]  A. Glavieux,et al.  Near Shannon limit error-correcting coding and decoding: Turbo-codes. 1 , 1993, Proceedings of ICC '93 - IEEE International Conference on Communications.

[8]  Heinrich Meyr,et al.  Real-time algorithms and VLSI architectures for soft output MAP convolutional decoding , 1995, Proceedings of 6th International Symposium on Personal, Indoor and Mobile Radio Communications.

[9]  M. Engels,et al.  Optimized MAP turbo decoder , 2000, 2000 IEEE Workshop on SiGNAL PROCESSING SYSTEMS. SiPS 2000. Design and Implementation (Cat. No.00TH8528).