Design of Clockless 32-bit Processor Core Using a Top-Down Based Asynchronous Circuit Design Flow

A clockless 32-bit processor core using a top-down based design flow for asynchronous circuits is introduced. We confirm the functionality of the proposed processor core at the pre-layout level with a 0.13 ㎛ CMOS technology. The applied tool is the first commercial EDA flow which is specialized in design of asynchronous circuits. In this tool, from describing behaviors of a system with a high level language, designers can implement fully asynchronous circuits to a pre-layout level.