A 16 Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling

This paper describes an adaptive bandwidth bus (ABB) architecture based on hybrid current/voltage mode repeaters for long global RC interconnect static busses that achieves high-data rates while minimizing the static power dissipation associated with current-mode signaling. Attaining a maximum aggregate bandwidth of 16 Gb/s (i.e., 1 Gb/s per line) across lossy on-chip interconnects spanning 1.75 cm in length, the bus core fabricated in 0.35 /spl mu/m CMOS technology dissipates approximately 93 mW with a supply of 2.5 V and signal activity of 0.5, equivalent to 5.71 pJ/bit. Experimental results using a 16-bit reference bus design that can be externally programmed to operate in voltage, current or adaptive modes indicate a 50% reduction in power dissipation over current-mode (CM) sensing, and an improvement in interconnection delay and signaling bandwidth of 35%-70% and 66% over voltage-mode (VM) sensing, respectively.

[1]  Evert Seevinck,et al.  Current-mode techniques for high-speed VLSI circuits with application to current sense amplifier for CMOS SRAM's , 1991 .

[2]  M. Bohr.  Interconnect scaling-the real limiter to high performance ULSI , 1995, Proceedings of International Electron Devices Meeting.

[3]  Todd M. Austin,et al.  The SimpleScalar tool set, version 2.0 , 1997, CARN.

[4]  Per Larsson-Edefors.  Investigation on maximal throughput of a CMOS repeater chain , 2000 .

[5]  Rizwan Bashirullah,et al.  Delay and power model for current-mode signaling in deep submicron global interconnects , 2002, Proceedings of the IEEE 2002 Custom Integrated Circuits Conference (Cat. No.02CH37285).

[6]  H. De Man,et al.  Methodology and experimental verification for substrate noise reduction in CMOS mixed-signal ICs with synchronous digital circuits , 2002, 2002 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.02CH37315).

[7]  Wentai Liu,et al.  Current-mode signaling in deep submicrometer global interconnects , 2003, IEEE Trans. Very Large Scale Integr. Syst..

[8]  Peter W. Cook,et al.  Low-power synchronous-to-asynchronous- to-synchronous interlocked pipelined CMOS circuits operating at 3.3-4.5 GHz , 2003 .

[9]  Wentai Liu,et al.  Low-power design methodology for an on-chip with adaptive bandwidth capability , 2003, Proceedings 2003. Design Automation Conference (IEEE Cat. No.03CH37451).

[10]  Wentai Liu,et al.  A hybrid current/voltage mode on-chip signaling scheme with adaptive bandwidth capability , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[11]  Atul Maheshwari,et al.  Differential current-sensing for on-chip interconnects , 2004, IEEE Transactions on Very Large Scale Integration (VLSI) Systems.

[12]  R. Bashirullah,et al.  A 16Gb/s adaptive bandwidth on-chip bus based on hybrid current/voltage mode signaling , 2004, 2004 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.04CH37525).