A Heterogeneous MPSoC with Hardware Supported Dynamic Task Scheduling for Software Defined Radio

In this paper, we present a fully programmable, heterogeneous single chip SDR platform with multimedia support. Running at 175 MHz, a peak performance of 40 GOPS is delivered while dissipating 1.5 W. The chip contains a hardware unit called CoreManager for run-time scheduling of tasks. The CoreManager solves the typical MPSoC programmability problem, improves energy efficiency and makes the platform scalable.

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