An IDDQ-fault location scheme

In this work, an IDDQ fault location scheme is proposed and implemented in a chip to locate a single faulty branch (either a VDD branch or a GND branch or both) with a three-pattern test by using a hardware approach, which can be applied to the redundant VLSI structure for yield enhancement in the repairable design. The fault model includes IDDQ fault with or without single stuck on/off fault in the added transistors. The yield analysis of the proposed scheme is also presented.

[1]  David L. Allen,et al.  Design aids and test results for laser-programmable logic arrays , 1990, Proceedings., 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors.

[2]  T. Y. Chang,et al.  An IDDQ-Fault Fab-Time Repairable CMOS SRAM Scheme , 1993 .

[3]  Tracy Larrabee,et al.  Testing for parametric faults in static CMOS circuits , 1990, Proceedings. International Test Conference 1990.

[4]  S. E. Schuster.  Multiple word/bit line redundancy for semiconductor memories , 1978 .

[5]  W.R. Moore,et al.  A review of fault-tolerant techniques for the enhancement of integrated circuit yield , 1986, Proceedings of the IEEE.

[6]  Tsin-Yuan Chang,et al.  Two schemes for detecting CMOS analog faults , 1992 .

[7]  J. M. Soden,et al.  Electrical properties and detection methods for CMOS IC defects , 1989, [1989] Proceedings of the 1st European Test Conference.

[8]  Richard W. Hamming,et al.  Error detecting and error correcting codes , 1950 .

[9]  Michele Favalli,et al.  Novel design for testability schemes for CMOS ICs , 1990 .

[10]  C. H. Stapper,et al.  Yield Model for Productivity Optimization of VLSI Memory Chips with Redundancy and Partially Good Product , 1980, IBM J. Res. Dev..

[11]  Wojciech Maly,et al.  Test generation for current testing , 1989, [1989] Proceedings of the 1st European Test Conference.

[12]  Robert C. Aitken,et al.  Fault Location with Current Monitoring , 1991, 1991, Proceedings. International Test Conference.

[13]  Vinod K. Agarwal,et al.  A diagnosis method using pseudo-random vectors without intermediate signatures , 1989, 1989 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[14]  Chin-Long Wey.  On yield consideration for the design of redundant programmable logic arrays , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[15]  Janusz Rajski,et al.  A method of fault analysis for test generation and fault diagnosis , 1988, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[16]  Melvin A. Breuer,et al.  Design and test rules for CMOS circuits to facilitate IDDQ testing of bridging faults , 1992, IEEE Trans. Comput. Aided Des. Integr. Circuits Syst..

[17]  Wojciech Maly,et al.  Built-in current testing-feasibility study , 1988, [1988] IEEE International Conference on Computer-Aided Design (ICCAD-89) Digest of Technical Papers.

[18]  Michael D. Ciletti,et al.  QUIETEST: a quiescent current testing methodology for detecting leakage faults , 1990, 1990 IEEE International Conference on Computer-Aided Design. Digest of Technical Papers.

[19]  Chin-Long Wey,et al.  Design of fault diagnosable and repairable PLA's , 1989 .

[20]  C. Stapper.  Defect density distribution for LSI yield calculations , 1973 .