论文信息 - Meeting the design challenges of nano-CMOS electronics: an introduction to an upcoming EPSRC pilot project

Meeting the design challenges of nano-CMOS electronics: an introduction to an upcoming EPSRC pilot project

This is a post print of a paper from UK e-Science All Hands Meeting 18th-21st September 2006 published by National e-Science Centre. http://www.allhands.org.uk/2006/

[1] A. Asenov,et al. Simulation Study of Individual and Combined Sources of Intrinsic Parameter Fluctuations in Conventional Nano-MOSFETs , 2006, IEEE Transactions on Electron Devices.

[2] Bian Zhi-xin,et al. Analyzing the Lithography Part of the International Technology Roadmap for Semiconductors (2005 Edition) , 2006 .

[3] Asen Asenov,et al. Impact of intrinsic parameter fluctuations in decanano MOSFETs on yield and functionality of SRAM cells , 2005 .

[4] R.M.D.A. Velghe,et al. CMOS device optimization for mixed-signal technologies , 2001, International Electron Devices Meeting. Technical Digest (Cat. No.01CH37224).

[5] Andrew R. Brown,et al. Simulation of intrinsic parameter fluctuations in decananometer and nanometer-scale MOSFETs , 2003 .

[6] A. Asenov,et al. Poly-Si-Gate-Related Variability in Decananometer MOSFETs With Conventional Architecture , 2007, IEEE Transactions on Electron Devices.

[7] B. Hornung,et al. An enhanced 90nm high performance technology with strong performance improvements from stress and mobility increase through simple process changes , 2004, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004..

[8] A. Ogura,et al. Sub-10-nm planar-bulk-CMOS devices using lateral junction control , 2003, IEEE International Electron Devices Meeting 2003.

[9] Asit Dan,et al. Web services agreement specification (ws-agreement) , 2004 .