Dual CLEFIA/AES Cipher Core on FPGA

In this paper a compact high throughput dual-cipher hardware structure is proposed, supporting the novel CLEFIA algorithm and the encryption standard AES. Currently, the more efficient and dedicated structures only allow to process the CLEFIA or the AES encryption algorithms. On the other hand, the existing multi-algorithm processors impose significantly higher area costs and are not able to achieve the throughputs of dedicated solutions. The presented work shows that by adequately scheduling and merging the processing structures, and with the proper use of the existing components in current FPGA technologies, it is possible to achieve a compact and efficient structure capable of computing the novel CLEFIA cipher while also supporting the well implanted AES cipher. Overall, the proposed structure allows for a throughput up to 1Gbps in feedback modes with low area cost, achieving identical efficiency metrics as the existing single cipher state of the art.

[1]  Jean-Didier Legat,et al.  Compact and efficient encryption/decryption module for FPGA implementation of the AES Rijndael very well suited for small embedded applications , 2004, International Conference on Information Technology: Coding and Computing, 2004. Proceedings. ITCC 2004..

[2]  Christof Paar,et al.  An instruction-level distributed processor for symmetric-key cryptography , 2005, IEEE Transactions on Parallel and Distributed Systems.

[3]  Ricardo Chaves,et al.  Compact CLEFIA Implementation on FPGAS , 2011, 2011 21st International Conference on Field Programmable Logic and Applications.

[4]  Simon Heron,et al.  Encryption: Advanced Encryption Standard (AES) , 2009 .

[5]  Odysseas G. Koufopavlou,et al.  Architectures and VLSI Implementations of the AES-Proposal Rijndael , 2002, IEEE Trans. Computers.

[6]  T. Suzaki,et al.  Cryptanalysis of CLEFIA using multiple impossible differentials , 2008, 2008 International Symposium on Information Theory and Its Applications.

[7]  Tomasz Kryjak,et al.  Pipeline implementation of the 128-bit block cipher CLEFIA in FPGA , 2009, 2009 International Conference on Field Programmable Logic and Applications.

[8]  Mohamed A. Abd El Ghany,et al.  Real-time efficient FPGA implementation of aes algorithm , 2013, 2013 IEEE International SOC Conference.

[9]  Fadi J. Kurdahi,et al.  MorphoSys: An Integrated Reconfigurable System for Data-Parallel and Computation-Intensive Applications , 2000, IEEE Trans. Computers.

[10]  Tim Güneysu,et al.  DSPs, BRAMs, and a Pinch of Logic: Extended Recipes for AES on FPGAs , 2010, TRETS.

[11]  Stamatis Vassiliadis,et al.  Reconfigurable memory based AES co-processor , 2006, Proceedings 20th IEEE International Parallel & Distributed Processing Symposium.

[12]  Jean-Jacques Quisquater,et al.  Implementation of the AES-128 on Virtex-5 FPGAs , 2008, AFRICACRYPT.

[13]  Ricardo Chaves,et al.  Secure partial dynamic reconfiguration with unsecured external memory , 2014, 2014 24th International Conference on Field Programmable Logic and Applications (FPL).

[14]  Kris Gaj,et al.  Very Compact FPGA Implementation of the AES Algorithm , 2003, CHES.

[15]  Tim Good,et al.  AES on FPGA from the Fastest to the Smallest , 2005, CHES.

[16]  Todd M. Austin,et al.  CryptoManiac: a fast flexible architecture for secure communication , 2001, Proceedings 28th Annual International Symposium on Computer Architecture.

[17]  Kyoji Shibutani,et al.  The 128-Bit Blockcipher CLEFIA (Extended Abstract) , 2007, FSE.

[18]  Qiang Liu,et al.  A 66.1 Gbps single-pipeline AES on FPGA , 2013, 2013 International Conference on Field-Programmable Technology (FPT).