To estimate the delay and area of a VLSI circuit before its
implementation demands a cost and delay model which
should be simple enough to allow a quick and therefore
cost-effective paper and pencil analysis. However, common
VLSI models are either to complicated resulting in
long simulation times or do not consider wire-delays, neglecting
their importance in sub-micron and nanotechnologies.
Paul and Seidel introduced such a technologyindependent
model in 1998 [Paul, Wolfgang J.; Seidel,
Peter-Michael: On the Complexity of Booth Recoding,
1998]. Based on this model, we will introduce a new VLSI
cost and delay model. It consists of two parts – a basic
technology-independent part based on reasonable enhancements
of the Paul and Seidel model and a technology-
specific part, where a specific technology can be
implied to get the effective circuit cost and delay. We analyze
the accuracy by comparing the cost and performance
of synthesized adder circuits with the results derived from
the model. The comparison reveals that the model closely
matches the cost and delay of the standard-cell and freely
placeable element-based implementations in the majority
of the tested circuits. Therefore, it could enhance existing
conventional VLSI models while retaining their simplicity.
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