The Effect of Compiler Optimizations on High-Level Synthesis-Generated Hardware

We consider the impact of compiler optimizations on the quality of high-level synthesis (HLS)-generated field-programmable gate array (FPGA) hardware. Using an HLS tool implemented within the state-of-the-art LLVM compiler, we study the effect of compiler optimizations on the hardware metrics of circuit area, execution cycles, FMax, and wall-clock time. We evaluate 56 different compiler optimizations implemented within LLVM and show that some optimizations significantly affect hardware quality. Moreover, we show that hardware quality is also affected by some optimization parameter values, as well as the order in which optimizations are applied. We then present a new HLS-directed approach to compiler optimizations, wherein we execute partial HLS and profiling at intermittent points in the optimization process and use the results to judiciously undo the impact of optimization passes predicted to be damaging to the generated hardware quality. Results show that our approach produces circuits with 16% better speed performance, on average, versus using the standard &mins;O3 optimization level.

[1]  Rudolf Eigenmann,et al.  Fast and effective orchestration of compiler optimizations for automatic performance tuning , 2006, International Symposium on Code Generation and Optimization (CGO'06).

[2]  Implementing FPGA Design with the OpenCL Standard , 2010 .

[3]  Michael F. P. O'Boyle,et al.  Milepost GCC: Machine Learning Enabled Self-tuning Compiler , 2011, International Journal of Parallel Programming.

[4]  Jason Helge Anderson,et al.  Impact of FPGA architecture on resource sharing in high-level synthesis , 2012, FPGA '12.

[5]  Hiroyuki Tomiyama,et al.  Proposal and Quantitative Analysis of the CHStone Benchmark Program Suite for Practical C-based High-level Synthesis , 2009, J. Inf. Process..

[6]  B. Ramakrishna Rau,et al.  Iterative Modulo Scheduling , 1996, International Journal of Parallel Programming.

[7]  Philippe Coussy,et al.  GAUT – A Free and Open Source High-Level Synthesis Tool for FPGA-Based Acceleration of Scientific Computing , 2010 .

[8]  Jason Helge Anderson,et al.  The Effect of Compiler Optimizations on High-Level Synthesis for FPGAs , 2013, 2013 IEEE 21st Annual International Symposium on Field-Programmable Custom Computing Machines.

[9]  Jason Helge Anderson,et al.  LegUp: An open-source high-level synthesis tool for FPGA-based processor/accelerator systems , 2013, TECS.

[10]  David I. August,et al.  Compiler optimization-space exploration , 2003, International Symposium on Code Generation and Optimization, 2003. CGO 2003..

[11]  Ching-Hsing Yu,et al.  SciNet: Lessons Learned from Building a Power-efficient Top-20 System and Data Centre , 2010 .

[12]  L. Almagor,et al.  Finding effective compilation sequences , 2004, LCTES '04.

[13]  Joseph A. Fisher,et al.  Trace Scheduling: A Technique for Global Microcode Compaction , 1981, IEEE Transactions on Computers.

[14]  Scott A. Mahlke,et al.  Effective compiler support for predicated execution using the hyperblock , 1992, MICRO 25.

[15]  Jason Cong,et al.  A Study on the Impact of Compiler Optimizations on High-Level Synthesis , 2012, LCPC.

[16]  Jason Cong,et al.  An efficient and versatile scheduling algorithm based on SDC formulation , 2006, 2006 43rd ACM/IEEE Design Automation Conference.

[17]  Nikil D. Dutt,et al.  SPARK: a high-level synthesis framework for applying parallelizing compiler transformations , 2003, 16th International Conference on VLSI Design, 2003. Proceedings..

[18]  Adrian Park,et al.  Designing Modular Hardware Accelerators in C with ROCCC 2.0 , 2010, 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines.