A fast parallel squarer based on divide-and-conquer

Fast and small squarers are needed in many applications such as image compression. A new family of high-performance parallel squarers based on the divide-and-conquer method is reported. Our main result was realized for the basis cases of the divide-and-conquer recursion by using optimized n-bit primitive squarers, where n is in the range of two to six. This method reduced the gate count and provided shorter critical paths. A chip implementing an 8-b squarer was designed, fabricated, and successfully tested, resulting in 24 million operations per second (MOPS) using a 2-/spl mu/m CMOS fabrication technology. This squarer had two additional features: increased number of squaring operations per unit circuit area and the potential for reduced power consumption per squaring operation.

[1]  Farid N. Najm,et al.  Transition density, a stochastic measure of activity in digital circuits , 1991, 28th ACM/IEEE Design Automation Conference.

[2]  Luigi Dadda.  Squarers for binary numbers in serial form , 1985, 1985 IEEE 7th Symposium on Computer Arithmetic (ARITH).

[3]  Tony M. Carter,et al.  Cell matrix methodologies for integrated circuit design , 1990, Integr..

[4]  Paul A. Wintz,et al.  Fast Multipliers , 1970, IEEE Transactions on Computers.

[5]  Christopher S. Wallace,et al.  A Suggestion for a Fast Multiplier , 1964, IEEE Trans. Electron. Comput..

[6]  G. Tiwary.  Below the half-micron mark , 1994, IEEE Spectrum.

[7]  Rajeev Jain,et al.  An integrated circuit design for pruned tree-search vector quantization encoding with an off-chip controller , 1992, IEEE Trans. Circuits Syst. Video Technol..

[8]  Homayoon Sam,et al.  A Generalized Multibit Recoding of Two's Complement Binary Numbers and Its Proof with Application in Multiplier Implementations , 1990, IEEE Trans. Computers.