A generalized symmetrical MLI topology with improved commutation

A generalized symmetrical multilevel inverter (MLI) topology with an essential feature of smooth commutation during the dead time for inductive loads is presented in this paper. It consists of a level generation unit (LGU) and polarity generation unit (PGU); Both LGU and PGU provide a freewheeling path for load current during the dead time for an inductive load which avoids large voltage spikes across the output. This topology can also generate the required number of levels at the output with a minimum number of components. As it requires fewer components, switching losses, installations space, and cost of the implementation are low. In this paper, a seven-level structure derived from the generalized topology is considered for detailed analysis. Further, to show the effectiveness of the proposed MLI topology over the existing symmetrical topologies in overcoming commutation problem, simulations were performed and are validated with experimental results. A comparative study is made in terms of power switches, power diodes, clamping capacitors, and driver circuits between traditional, recent, and proposed topologies.