An accurate semi-analytical framework for full-chip TSV-induced stress modeling

TSV-induced stress is an important issue in 3D IC design since it leads to serious reliability problems and influences device performance. Existing finite element method can provide accurate analysis for the stress of simple TSV placement, but is not scalable to larger designs due to its expensive memory consumption and high run time. On the contrary, linear superposition method is efficient to analyze stress in full-chip scale, but sometimes it fails to provide an accurate estimation since it neglects the stress induced by interactions between TSVs. In this paper we propose an accurate two-stage semi-analytical framework for fullchip TSV-induced stress modeling. In addition to the linear superposition, we characterize the stress induced by interactions between TSVs to provide more accurate full-chip modeling. Experimental results demonstrate that the proposed framework can significantly improve the accuracy of linear superposition method with reasonable overhead in run time.

[1]  Suk-kyu Ryu,et al.  Thermo-mechanical reliability of 3-D ICs containing through silicon vias , 2009, 2009 59th Electronic Components and Technology Conference.

[2]  C. K. Lee,et al.  Structural design, process, and reliability of a wafer-level 3D integration scheme with Cu TSVs based on micro-bump/adhesive hybrid wafer bonding , 2012, 2012 IEEE 62nd Electronic Components and Technology Conference.

[3]  Yuan Xie,et al.  Analysis and mitigation of lateral thermal blockage effect of through-silicon-via in 3D IC designs , 2011, IEEE/ACM International Symposium on Low Power Electronics and Design.

[4]  Li Yu,et al.  Methodology for analysis of TSV stress induced transistor variation and circuit performance , 2012, Thirteenth International Symposium on Quality Electronic Design (ISQED).

[5]  Suk-kyu Ryu,et al.  Impact of Near-Surface Thermal Stresses on Interfacial Reliability of Through-Silicon Vias for 3-D Interconnects , 2011, IEEE Transactions on Device and Materials Reliability.

[6]  N. Muskhelishvili.  Some basic problems of the mathematical theory of elasticity , 1953 .

[7]  Xi Liu,et al.  Full-chip through-silicon-via interfacial crack analysis and optimization for 3D IC , 2011, 2011 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[8]  Jae-Seok Yang,et al.  Stress-driven 3D-IC placement with TSV keep-out zone and regularity study , 2010, 2010 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[9]  Sung Kyu Lim,et al.  Chip/package co-analysis of thermo-mechanical stress and reliability in TSV-based 3D ICs , 2012, DAC Design Automation Conference 2012.

[10]  Sung Kyu Lim,et al.  TSV Stress-Aware Full-Chip Mechanical Reliability Analysis and Optimization for 3-D IC , 2011, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems.

[11]  Luca Benini,et al.  Design Issues and Considerations for Low-Cost 3-D TSV IC Technology , 2010, IEEE Journal of Solid-State Circuits.

[12]  C. Zhang,et al.  Characterization and Design of Through-Silicon Via Arrays in Three-Dimensional ICs Based on Thermomechanical Modeling , 2011, IEEE Transactions on Electron Devices.

[13]  Jae-Seok Yang,et al.  TSV stress aware timing analysis with applications to 3D-IC layout optimization , 2010, Design Automation Conference.

[14]  Jian-Qiang Lu,et al.  Modeling Thermal Stresses in 3-D IC Interwafer Interconnects , 2006, IEEE Transactions on Semiconductor Manufacturing.

[15]  Paresh Limaye,et al.  Design issues and considerations for low-cost 3D TSV IC technology , 2010, 2010 IEEE International Solid-State Circuits Conference - (ISSCC).

[16]  Sachin S. Sapatnekar,et al.  A holistic analysis of circuit timing variations in 3D-ICs with thermal and TSV-induced stress considerations , 2012, 2012 IEEE/ACM International Conference on Computer-Aided Design (ICCAD).

[17]  Ying Ying Lim,et al.  Numerical modeling of through silicon via (TSV) stacked module with micro bump interconnect for biomedical device , 2010, 2010 12th Electronics Packaging Technology Conference.

[18]  David Z. Pan,et al.  A fast simulation framework for full-chip thermo-mechanical stress and reliability analysis of through-silicon-via based 3D ICs , 2011, 2011 IEEE 61st Electronic Components and Technology Conference (ECTC).