On the Case of Using Aggregated Page Programming for Future MLC NAND Flash Memory
暂无分享,去创建一个
Nanning Zheng | Tong Zhang | Hui Han | Guiqiang Dong | Wenzhe Zhao | Nanning Zheng | Wenzhe Zhao | Guiqiang Dong | Tong Zhang | Hui Han
[1] A. Inoue,et al. A 70 nm 16 Gb 16-Level-Cell NAND flash Memory , 2008, IEEE Journal of Solid-State Circuits.
[2] Yan Li,et al. A 16 Gb 3-Bit Per Cell (X3) NAND Flash Memory on 56 nm Technology With 8 MB/s Write Rate , 2009, IEEE Journal of Solid-State Circuits.
[3] Khanh Nguyen,et al. A 5.6MB/s 64Gb 4b/Cell NAND Flash memory in 43nm CMOS , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[4] A. Visconti,et al. Random Telegraph Noise Effect on the Programmed Threshold-Voltage Distribution of Flash Memories , 2009, IEEE Electron Device Letters.
[5] Ogawa,et al. Generalized diffusion-reaction model for the low-field charge-buildup instability at the Si-SiO2 interface. , 1995, Physical review. B, Condensed matter.
[6] Yeong-Taek Lee,et al. A Zeroing Cell-to-Cell Interference Page Architecture With Temporary LSB Storing and Parallel MSB Program Scheme for MLC NAND Flash Memories , 2008, IEEE Journal of Solid-State Circuits.
[7] Haitao Liu,et al. 3D Simulation Study of Cell-Cell Interference in Advanced NAND Flash Memory , 2009, 2009 IEEE Workshop on Microelectronics and Electron Devices.
[8] A. Lacaita,et al. First evidence for injection statistics accuracy limitations in NAND Flash constant-current Fowler-Nordheim programming , 2007, 2007 IEEE International Electron Devices Meeting.
[9] Young-Ho Lim,et al. A 3.3 V 32 Mb NAND flash memory with incremental step pulse programming scheme , 1995 .
[10] Tong Zhang,et al. Using Data Postcompensation and Predistortion to Tolerate Cell-to-Cell Interference in MLC nand Flash Memory , 2010, IEEE Transactions on Circuits and Systems I: Regular Papers.
[11] Roberto Bez,et al. Introduction to flash memory , 2003, Proc. IEEE.
[12] P. Kalavade,et al. Flash EEPROM threshold instabilities due to charge trapping during program/erase cycling , 2004, IEEE Transactions on Device and Materials Reliability.
[13] Jungdal Choi,et al. Effects of floating-gate interference on NAND flash memory cell operation , 2002 .
[14] Kinam Kim,et al. Effects of interface trap generation and annihilation on the data retention characteristics of flash memory cells , 2004 .
[15] J. V. Houdt,et al. Write/erase degradation in source side injection flash EEPROM's: characterization techniques and wearout mechanisms , 1995 .
[16] William Ryan,et al. Channel Codes by William Ryan , 2009 .
[17] A. Lacaita,et al. Investigation of the threshold voltage instability after distributed cycling in nanoscale NAND Flash memory arrays , 2010, 2010 IEEE International Reliability Physics Symposium.
[18] Jianbo Yang,et al. Analytical reaction-diffusion model and the modeling of nitrogen-enhanced negative bias temperature instability , 2006 .
[19] Kinam Kim,et al. Future memory technology: challenges and opportunities , 2008, 2008 International Symposium on VLSI Technology, Systems and Applications (VLSI-TSA).
[20] William Ryan,et al. Channel Codes: Classical and Modern , 2009 .
[21] Shu Lin,et al. Channel Codes: Classical and Modern , 2009 .
[22] Mahdiar Hosein Ghadiry,et al. DLPA: Discrepant Low PDP 8-Bit Adder , 2013, Circuits Syst. Signal Process..
[23] Hyung-Kyu Lim,et al. A 117-mm2 3.3-V only 128-Mb multilevel NAND flash memory for mass storage applications , 1996, IEEE J. Solid State Circuits.
[24] C. Hu,et al. Random telegraph noise in flash memories - model and technology scaling , 2007, 2007 IEEE International Electron Devices Meeting.
[25] Javier Valls-Coquillat,et al. Architecture of Generalized Bit-Flipping Decoding for High-Rate Non-binary LDPC Codes , 2013, Circuits Syst. Signal Process..
[26] Hong Ding,et al. A 113mm2 32Gb 3b/cell NAND flash memory , 2009, 2009 IEEE International Solid-State Circuits Conference - Digest of Technical Papers.
[27] Hong Yang,et al. Reliability Issues and Models of sub-90nm NAND Flash Memory Cells , 2006, 2006 8th International Conference on Solid-State and Integrated Circuit Technology Proceedings.
[28] B. Riccò,et al. High‐field‐induced voltage‐dependent oxide charge , 1986 .
[29] Roberto Bez,et al. Failure mechanisms of flash cell in program/erase cycling , 1994, Proceedings of 1994 IEEE International Electron Devices Meeting.
[30] K. Takeuchi,et al. A double-level-V/sub th/ select gate array architecture for multi-level NAND flash memories , 1995, Digest of Technical Papers., Symposium on VLSI Circuits..
[31] H. Belgal,et al. Recovery Effects in the Distributed Cycling of Flash Memories , 2006, 2006 IEEE International Reliability Physics Symposium Proceedings.